27.7.8 Voltage Regulator System (VREG) Control

Note: During normal operation, all voltage regulators that are in use must be left in the On state to allow for the proper transition between different low-power or standby states.
Table 27-10. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: VREGCTRL
Offset: 0x001C
Reset: 0x00000004
Property: PAC Write-Protection

Bit 3130292827262524 
        AVREGSTDBY 
Access R/W 
Reset 0 
Bit 2322212019181716 
        AVREGEN 
Access R/W 
Reset 0 
Bit 15141312111098 
       CPEN[1:0] 
Access R/WR/W 
Reset 00 
Bit 76543210 
   LVHIBLVSTDBY OFFSTDBY   
Access R/W/HCR/W/HCR/W 
Reset 000 

Bit 24 – AVREGSTDBY Additional Voltage Regulator Configuration

ValueDescription
0x0USB regulator is off in Sleep, Standby, Hibernate or Backup mode.
0x1USB regulator is ON in Standby mode if the AVREGEN bit is set.

It is OFF in Hibernate or Backup mode.

Bit 16 – AVREGEN Additional Voltage Regulator Enabled

ValueDescription
0x0USB regulator is disabled (Default)
0x1USB regulator is Enabled

Bits 9:8 – CPEN[1:0]  Analog Peripheral Charge Pump Enabled

ValueDescriptionRequirements
0x0All charge pumps disabled.AVDD ≥ 2.5v
0x1Enable charge pump for I/O analog mux and Analog Comparator (AC)AVDD < 2.5v
---Reserved
0x3Enable charge pumps for I/O, AC, ADC, and PTC
Note:
  1. When AVDD < 2.5v the corresponding appropriate CPEN must be enabled.
  2. Users must have previously enabled the charge pump clocks defined in Configuration Register 5, FUCFG5.

Bit 5 – LVHIB Low Voltage Hibernate Enable

Note: LVHIB must always be forced to 1.
ValueDescription
0x0In Hibernate mode, VDDCORE_BU and VDDCORE_RAM are set to 1.2v.
0x1In Hibernate mode, VDDCORE_BU and VDDCORE_RAM are set to 0.8v

Bit 4 – LVSTDBY Low Voltage Standby Enable

ValueDescription
0x0In Standby mode, VDDCORE_BU, VDDCORE_RAM, VDDCORE_SW and optionally VDDCOREUSB/PLL are set to 1.2v.
0x1In Standby mode, VDDCORE_BU, VDDCORE_RAM, VDDCORE_SW and operationally VDDCOREUSB/PLL are set to 0.8v.

Bit 2 – OFFSTDBY Off in Standby Control VREGSW 0 and 1

ValueDescription
0x0In Standby mode, VREGSW 0,1 are OFF
0x1In standby mode, VREGSW 0,1 are ON