18.1 Clock Distribution

Figure 18-1. Clock Distribution Block Diagram

The PIC32CK SG/GC clock system features are as follows:

  • Clock sources, that is oscillators controlled by OSCCTRL and OSC32KCTRL:
    • A clock source provides a time base that is used by other components, such as Generic Clock Generators. For example, clock sources are the internal 48 MHz DFLL48M, Ultra Low-power 32 kHz RC oscillator, OSCULP32K, PLL and external oscillators XOSC and XOSC32K.
  • Generic Clock Controller (GCLK), which generates, controls, and distributes asynchronous clocks consisting of the following:
    • Generic Clock Generators: These have programmable prescalers that can use any of the system clock sources. The Generic Clock Generator 0 generates the clock signal GCLK_MAIN, which is used by the CPU and Data Ram Tightly Coupled Memory, which in turn generates synchronous clocks.
    • Generic Clocks: These are clock signals generated by Generic Clock Generators. They are the Peripheral Channels and serve as clocks for the peripherals of the system. Multiple instances of a peripheral will typically have a separate Generic Clock.
  • Main Clock Controller (MCLK)
    • The MCLK generates and controls the synchronous clocks for the system. This includes the CPU, bus clocks (AHB (Advanced High-performance Bus), and APB (Advanced Peripheral Bus) ), as well as the Special Function Register interfaces of the peripherals. It contains clock masks that can turn on/off the user interface of a peripheral as well as prescalers for the CPU and bus clocks.

The following figure illustrates an example, where SERCOM0 is clocked by the DFLL48M (RC 48 MHz) in Open-Loop mode. The DFLL48M is enabled, the Generic Clock Generator n uses the DFLL48M as its clock source and feeds into Peripheral Channel 19. The Generic Clock, also called GCLK_SERCOM0_CORE, is connected to SERCOM0 that supplies the functional logic clocks. The SERCOM0 interface, clocked by CLK_SERCOM0_APB, has been unmasked in the MCLK APB SERCOM0 mask register, MCLK.CLKMSK2.MSK7.

Figure 18-2. Example of SERCOM_0 Clock
To customize the clock distribution, refer to these registers and bit fields:
  • The source oscillator for a generic clock generator 'n' is selected by writing to the Source bit field in the Generator Control n, (n = 0-15), register (GCLK.GENCTRLn.SRC).
  • A Peripheral Channel m can be configured to use a specific Generic Clock Generator by writing to the Generic Clock Generator bit field in the respective Peripheral Channel m register (GCLK.PCHCTRLm.GEN).
  • The Peripheral Channel number, m, is fixed for a given peripheral. See the Mapping table in the description of GCLK.PCHCTRLm, (i.e., GCLK Chapter).
  • The AHB/APB/AIX Peripheral BUS clocks are enabled and disabled by writing to the respective bit in the AHB/APB/AIX Mask register. The AHB/APB/AIX clocks are enabled and disabled by writing to the respective bit in the AHB/APB/AIX Mask register (MCLK.CLKMSK[0,1,2,3].MSKn). They are enabled by default on reset.