30.7.16 Non-secure Interrupt
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | NONSEC |
| Offset: | 0x40 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Write-Secure |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| NMI | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EXTINT[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EXTINT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – NMI Non-Secure Non-Maskable Interrupt
This bit enables the non-secure mode of NMI.
The registers whose content is set in non-secure mode by NONSEC.NMI are NMICTRL and NMIFLAG registers.
| Value | Description |
|---|---|
| 0 | NMI is secure. |
| 1 | NMI is non-secure. |
Bits 15:0 – EXTINT[15:0] Non-Secure External Interrupt
The bit x of EXTINT enables the non-secure mode of EXTINTx.
The registers whose EXTINT bit or bitfield x is set in non-secure mode by NONSEC.EXTINTx are EVCTRL, ASYNCH, IDEBOUNCEN, INTENCLR, INTENSET, INTFLAG and CONFIG registers.
| Value | Description |
|---|---|
| 0 | EXTINTx is secure. |
| 1 | EXTINTx is non-secure. |
