28.6.1 Control A

Table 28-4. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CTRLA
Offset:	0x0000
Reset:	0x00
Property:	PAC Write-Protection


Bit	7	6	5	4	3	2	1	0
						IORET
Access						R/W
Reset						0

Bit 2 – IORET I/O Retention

When entering Hibernate or Backup mode, I/O ports are powered off but the pin configurations are retained. When the device exits either mode, pin configurations are either released or stretched, based on this bit:

Value	Description
0x0	When the device exits the Hibernate or Backup mode, pin configurations are released and driven to the current values defined pin’s PORT registers.
0x1	When the device exits the Hibernate or Backup mode, pin configurations are retained until the IORET bit is cleared. This allows the pins to retain their states until the application has programmed new PORT values and then clears IORET.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.