7.3.2 Starting of Clocks

Once the power has stabilized and the internal Reset is released, the device will use a 48 MHz clock by default. The clock source for this clock signal is DFLL48M, which is enabled after a reset by default. This is also the default time base for Generic Clock Generator 0. In turn, Generator 0 provides the main clock GCLK_MAIN which is used by the Main Clock module (MCLK).

Some synchronous system clocks are active after start-up, allowing software execution. Refer to the Clock Mask Registers section in the Main Clock (MCLK) chapter for a list of clocks that are running by default. Synchronous system clocks that are running receive the 48 MHz clock from Generic Clock Generator 0. Other generic clocks are disabled.