During debugging, if data is changed in the Watch Window, it will increase the number
of cycle times. For example, if you change an SFR or variable in a Watch Window while
stepping through code, it forces the program to flush the pipeline of uncompleted steps
and to restart. This adds extra cycles resulting in an inaccurate execution time.
Simulator does not support the CRC calculation with DMA.
DMA transfer will occur even for cached variables in PIC32 devices.
Multiply and Divide latency is not implemented in the simulator at this time.
The back to back multiply operation does not stall the pipeline.
The load and store instruction does not stall the pipeline, which may result in
incorrect results under certain conditions.
Features not simulated:
Bus Matrix Configuration
CAN
Code protection
Comparator voltage reference
Crypto engine
Dual Panel functionality
Enhanced Parallel Master Port (EPMP)
Oscillator I/O control
Oscillator switching
PLL multiplier and divider
Power saving (Sleep and Idle)
modes.
Pre-fetch CACHE
Real Time Clock and Calendar
Separate Peripheral Bus clock. (PB clock is same as CPU clock.)
Serial I/O (I2C and SPI). However,
SSPSTAT register is readable and writable
