32.6.4 DMA, Interrupts and Events
| Condition | Request | ||
|---|---|---|---|
| DMA | Interrupt | Event | |
| Data Register Empty (DRE) | Yes (request cleared when data is written) | Yes | NA |
| Receive Complete (RXC) | Yes (request cleared when data is read) | Yes | |
| Transmit Complete (TXC) | NA | Yes | |
| Receive Start (RXS) | NA | Yes | |
| Clear to Send Input Change (CTSIC) | NA | Yes | |
| Receive Break (RXBRK) | NA | Yes | |
| Error (ERROR) | NA | Yes | |