32.6.4 DMA, Interrupts and Events

Table 32-4. Module Request for SERCOM USART
ConditionRequest
DMA Interrupt Event
Data Register Empty (DRE)Yes

(request cleared when data is written)

YesNA
Receive Complete (RXC)Yes

(request cleared when data is read)

Yes
Transmit Complete (TXC)NAYes
Receive Start (RXS)NAYes
Clear to Send Input Change (CTSIC)NAYes
Receive Break (RXBRK)NAYes
Error (ERROR)NAYes