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SAM L21 Family Data Sheet SAM L21
Introduction
Features
1 Description
2 Configuration Summary
3 Ordering Information
3.1 SAM L21J
3.2 SAM L21G
3.3 SAM L21E
3.4 Device Identification
4 Block Diagram
5 Pinout
5.1 SAM L21J
5.2 SAM L21J WLCSP64
5.3 SAM L21G
5.4 SAM L21E
6 Signal Descriptions List
7 I/O Multiplexing and Considerations
7.1 Multiplexed Signals
7.2 Other Functions
8 Analog Connections of Peripherals
8.1 Block Diagram
8.2 Analog Connections
8.3 Reference Voltages
8.4 Analog ONDEMAND Function
9 Power Supply and Start-Up Considerations
9.1 Power Domain Overview
9.2 Power Supply Considerations
9.3 Power-Up
9.4 Power-On Reset and Brown-Out Detector
9.5 Performance Level Overview
10 Product Mapping
11 Memories
11.1 Embedded Memories
11.2 Physical Memory Map
11.3 NVM User Row Mapping
11.4 NVM Software Calibration Area Mapping
11.5 NVM Temperature Log Row
11.6 Serial Number
12 Processor and Architecture
12.1 Cortex M0+ Processor
12.2 Nested Vector Interrupt Controller
12.3 Micro Trace Buffer
12.4 High-Speed Bus System
13 PAC - Peripheral Access Controller
13.1 Overview
13.2 Features
13.3 Block Diagram
13.4 Product Dependencies
13.5 Functional Description
13.6 Register Summary
13.7 Register Description
14 Peripherals Configuration Summary
15 DSU - Device Service Unit
15.1 Overview
15.2 Features
15.3 Block Diagram
15.4 Signal Description
15.5 Product Dependencies
15.6 Debug Operation
15.7 Chip Erase
15.8 Programming
15.9 Intellectual Property Protection
15.10 Device Identification
15.11 Functional Description
15.12 Register Summary
15.13 Register Description
16 Clock System
16.1 Clock Distribution
16.2 Synchronous and Asynchronous Clocks
16.3 Register Synchronization
16.4 Enabling a Peripheral
16.5 On Demand Clock Requests
16.6 Power Consumption vs. Speed
16.7 Clocks after Reset
17 GCLK - Generic Clock Controller
17.1 Overview
17.2 Features
17.3 Block Diagram
17.4 Signal Description
17.5 Product Dependencies
17.6 Functional Description
17.7 Sleep Mode Operation
17.8 Additional Features
17.9 Register Summary
17.10 Register Description
18 MCLK – Main Clock
18.1 Overview
18.2 Features
18.3 Block Diagram
18.4 Signal Description
18.5 Product Dependencies
18.6 Functional Description
18.7 Register Summary - MCLK
18.8 Register Description
19 RSTC – Reset Controller
19.1 Overview
19.2 Features
19.3 Block Diagram
19.4 Signal Description
19.5 Product Dependencies
19.6 Functional Description
19.7 Register Summary
19.8 Register Description
20 PM – Power Manager
20.1 Overview
20.2 Features
20.3 Block Diagram
20.4 Signal Description
20.5 Product Dependencies
20.6 Functional Description
20.7 Register Summary
20.8 Register Description
21 OSCCTRL – Oscillators Controller
21.1 Overview
21.2 Features
21.3 Block Diagram
21.4 Signal Description
21.5 Product Dependencies
21.6 Functional Description
21.7 Register Summary
21.8 Register Description
22 OSC32KCTRL – 32KHz Oscillators Controller
22.1 Overview
22.2 Features
22.3 Block Diagram
22.4 Signal Description
22.5 Product Dependencies
22.6 Functional Description
22.7 Register Summary
22.8 Register Description
23 SUPC – Supply Controller
23.1 Overview
23.2 Features
23.3 Block Diagram
23.4 Signal Description
23.5 Product Dependencies
23.6 Functional Description
23.7 Register Summary
23.8 Register Description
24 WDT – Watchdog Timer
24.1 Overview
24.2 Features
24.3 Block Diagram
24.4 Signal Description
24.5 Product Dependencies
24.6 Functional Description
24.7 Register Summary
24.8 Register Description
25 RTC – Real-Time Counter
25.1 Overview
25.2 Features
25.3 Block Diagram
25.4 Signal Description
25.5 Product Dependencies
25.6 Functional Description
25.7 Register Summary - COUNT32
25.8 Register Description - COUNT32
25.9 Register Summary - COUNT16
25.10 Register Description - COUNT16
25.11 Register Summary - CLOCK
25.12 Register Description - CLOCK
26 DMAC – Direct Memory Access Controller
26.1 Overview
26.2 Features
26.3 Block Diagram
26.4 Signal Description
26.5 Product Dependencies
26.6 Functional Description
26.7 Register Summary
26.8 Register Description
26.9 Register Summary - LP SRAM
26.10 Register Description - LP SRAM
27 EIC – External Interrupt Controller
27.1 Overview
27.2 Features
27.3 Block Diagram
27.4 Signal Description
27.5 Product Dependencies
27.6 Functional Description
27.7 Register Summary
27.8 Register Description
28 NVMCTRL – Non-Volatile Memory Controller
28.1 Overview
28.2 Features
28.3 Block Diagram
28.4 Signal Description
28.5 Product Dependencies
28.6 Functional Description
28.7 Register Summary
28.8 Register Description
29 PORT - I/O Pin Controller
29.1 Overview
29.2 Features
29.3 Block Diagram
29.4 Signal Description
29.5 Product Dependencies
29.6 Functional Description
29.7 Register Summary
29.8 Register Description
30 EVSYS – Event System
30.1 Overview
30.2 Features
30.3 Block Diagram
30.4 Signal Description
30.5 Product Dependencies
30.6 Functional Description
30.7 Register Summary
30.8 Register Description
31 SERCOM – Serial Communication Interface
31.1 Overview
31.2 Features
31.3 Block Diagram
31.4 Signal Description
31.5 Product Dependencies
31.6 Functional Description
32 SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter
32.1 Overview
32.2 USART Features
32.3 Block Diagram
32.4 Signal Description
32.5 Product Dependencies
32.6 Functional Description
32.7 Register Summary
32.8 Register Description
33 SERCOM SPI – SERCOM Serial Peripheral Interface
33.1 Overview
33.2 Features
33.3 Block Diagram
33.4 Signal Description
33.5 Product Dependencies
33.6 Functional Description
33.7 Register Summary
33.8 Register Description
34 SERCOM I2C – SERCOM Inter-Integrated Circuit
34.1 Overview
34.2 Features
34.3 Block Diagram
34.4 Signal Description
34.5 Product Dependencies
34.6 Functional Description
34.7 Register Summary - I2C Client
34.8 Register Description - I2C Client
34.9 Register Summary - I2C Host
34.10 Register Description - I2C Host
35 TC – Timer/Counter
35.1 Overview
35.2 Features
35.3 Block Diagram
35.4 Signal Description
35.5 Product Dependencies
35.6 Functional Description
35.7 Register Description
36 TCC – Timer/Counter for Control Applications
36.1 Overview
36.2 Features
36.3 Block Diagram
36.4 Signal Description
36.5 Product Dependencies
36.6 Functional Description
36.7 Register Summary
36.8 Register Description
37 TRNG – True Random Number Generator
37.1 Overview
37.2 Features
37.3 Block Diagram
37.4 Signal Description
37.5 Product Dependencies
37.6 Functional Description
37.7 Register Summary
37.8 Register Description
38 AES – Advanced Encryption Standard
38.1 Overview
38.2 Features
38.3 Block Diagram
38.4 Signal Description
38.5 Product Dependencies
38.6 Functional Description
38.7 Register Summary
38.8 Register Description
39 USB – Universal Serial Bus
39.1 Overview
39.2 Features
39.3 USB Block Diagram
39.4 Signal Description
39.5 Product Dependencies
39.6 Functional Description
39.7 Communication Device Host Register Summary
39.8 Communication Device Host Register Description
39.9 Device Registers - Common -Register Summary
39.10 Device Registers - Common
39.11 Device Endpoint Register Summary
39.12 Device Endpoint Register Description
39.13 Endpoint Descriptor Structure
39.14 Device Endpoint RAM Register Summary
39.15 Device Endpoint RAM Register Description
39.16 Host Registers - Common - Register Summary
39.17 Host Registers - Common - Register Description
39.18 Host Registers - Pipe - Register Summary
39.19 Host Registers - Pipe - Register Description
39.20 Pipe Descriptor Structure
39.21 Host Registers - Pipe RAM - Register Summary
39.22 Host Registers - Pipe RAM - Register Description
40 CCL – Configurable Custom Logic
40.1 Overview
40.2 Features
40.3 Block Diagram
40.4 Signal Description
40.5 Product Dependencies
40.6 Functional Description
40.7 Register Summary
40.8 Register Description
41 Operational Amplifier Controller (OPAMP)
41.1 Overview
41.2 Features
41.3 Block Diagram
41.4 Signal Description
41.5 Product Dependencies
41.6 Functional Description
41.7 Register Summary
41.8 Register Description
42 ADC – Analog-to-Digital Converter
42.1 Overview
42.2 Features
42.3 Block Diagram
42.4 Signal Description
42.5 Product Dependencies
42.6 Functional Description
42.7 Register Summary
42.8 Register Description
43 AC – Analog Comparators
43.1 Overview
43.2 Features
43.3 Block Diagram
43.4 Signal Description
43.5 Product Dependencies
43.6 Functional Description
43.7 Register Summary
43.8 Register Description
44 DAC – Digital-to-Analog Converter
44.1 Overview
44.2 Features
44.3 Block Diagram
44.4 Signal Description
44.5 Product Dependencies
44.6 Functional Description
44.7 Register Summary
44.8 Register Description
45 PTC - Peripheral Touch Controller
45.1 Overview
45.2 Features
45.3 Block Diagram
45.4 Signal Description
45.5 Product Dependencies
45.6 Functional Description
46 Electrical Characteristics
46.1 Disclaimer
46.2 Absolute Maximum Ratings
46.3 General Operating Ratings
46.4 Supply Characteristics
46.5 Maximum Clock Frequencies
46.6 Power Consumption
46.7 Wake-Up Time
46.8 I/O Pin Characteristics
46.9 Injection Current
46.10 Analog Characteristics
46.11 NVM Characteristics
46.12 Oscillators Characteristics
46.13 Timing Characteristics
46.14 USB Characteristics
47 Electrical Characteristics - Extended Temperature Range 105°C
47.1 Disclaimer
47.2 General Operating Ratings - 105°C
47.3 Power Consumption
47.4 I/O Pin Characteristics
47.5 Injection Current - 105°C
47.6 Analog Characteristics
47.7 NVM Characteristics
47.8 Oscillators Characteristics
47.9 Timing Characteristics
48 Typical Characteristics
48.1 Power Consumption over Temperature in Sleep Modes
49 Appendix A
49.1 SIL 2-Enabled Functional Safety Devices
50 Packaging Information
50.1 Thermal Considerations
50.2 Package Drawings
50.3 Soldering Profile
51 Schematic Checklist
51.1 Introduction
51.2 Power Supply
51.3 External Analog Reference Connections
51.4 External Reset Circuit
51.5 Unused or Unconnected Pins
51.6 Clocks and Crystal Oscillators
51.7 Programming and Debug Ports
51.8 USB Interface
52 Conventions
52.1 Numerical Notation
52.2 Memory Size and Type
52.3 Frequency and Time
52.4 Registers and Bits
53 Acronyms and Abbreviations
54 Datasheet Revision History
54.1 Rev. E - 07/2023
54.2 Rev. D - 06/2023
54.3 Rev. C - 03/2020
54.4 Rev B - 02/2020
54.5 Rev. A - 02/2017
54.6 Rev J - 06/2016
54.7 Rev I - 02/2016
54.8 Rev H - 12/2015
54.9 Rev G - 11/2015
54.10 Rev F - 09/2015
54.11 Rev E - 07/2015
54.12 Rev D - 06/2015
54.13 Rev C - 03/2015
54.14 Rev B - 02/2015
54.15 Rev A - 01/2015
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