17.10.4 Peripheral Channel Control
| Name: | PCHCTRLm |
| Offset: | 0x80 + m*0x04 [m=0..34] |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WRTLOCK | CHEN | GEN[3:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 7 – WRTLOCK Write Lock
After this bit is set to '1', further writes to the PCHCTRLm register will be discarded. The control register of the corresponding Generator n (GENCTRLn), as assigned in PCHCTRLm.GEN, will also be locked. It can only be unlocked by a Power Reset.
Note that Generator 0 cannot be locked.
| Value | Description |
|---|---|
| 0 | The Peripheral Channel register and the associated Generator register are not locked |
| 1 | The Peripheral Channel register and the associated Generator register are locked |
Bit 6 – CHEN Channel Enable
This bit is used to enable and disable a Peripheral Channel.
| Value | Description |
|---|---|
| 0 | The Peripheral Channel is disabled |
| 1 | The Peripheral Channel is enabled |
Bits 3:0 – GEN[3:0] Generator Selection
This bit field selects the Generator to be used as the source of a peripheral clock, as shown in the table below:
| Value | Description |
|---|---|
| 0x0 | Generic Clock Generator 0 |
| 0x1 | Generic Clock Generator 1 |
| 0x2 | Generic Clock Generator 2 |
| 0x3 | Generic Clock Generator 3 |
| 0x4 | Generic Clock Generator 4 |
| 0x5 | Generic Clock Generator 5 |
| 0x6 | Generic Clock Generator 6 |
| 0x7 | Generic Clock Generator 7 |
| 0x8 | Generic Clock Generator 8 |
| 0x9 - 0xF | Reserved |
| Reset | PCHCTRLm.GEN | PCHCTRLm.CHEN | PCHCTRLm.WRTLOCK |
|---|---|---|---|
| Power Reset | 0x0 | 0x0 | 0x0 |
| User Reset |
If WRTLOCK = 0 : 0x0 If WRTLOCK = 1: no change |
If WRTLOCK = 0 : 0x0 If WRTLOCK = 1: no change | No change |
A Power Reset will reset all the PCHCTRLm registers.
A User Reset will reset a PCHCTRL if WRTLOCK=0, or else, the content of that PCHCTRL remains unchanged.
PCHCTRL register Reset values are shown in the table PCHCTRLm Mapping.
| index(m) | Name | Description |
|---|---|---|
| 0 | GCLK_DFLL48M_REF | DFLL48M Reference |
| 1 | GCLK_DPLL | FDPLL96M input clock source for reference |
| 2 | GCLK_DPLL_32K | FDPLL96M 32kHz clock for FDPLL96M internal lock timer |
| 3 | GCLK_EIC | EIC |
| 4 | GCLK_USB | USB |
| 5 | GCLK_EVSYS_CHANNEL_0 | EVSYS_CHANNEL_0 |
| 6 | GCLK_EVSYS_CHANNEL_1 | EVSYS_CHANNEL_1 |
| 7 | GCLK_EVSYS_CHANNEL_2 | EVSYS_CHANNEL_2 |
| 8 | GCLK_EVSYS_CHANNEL_3 | EVSYS_CHANNEL_3 |
| 9 | GCLK_EVSYS_CHANNEL_4 | EVSYS_CHANNEL_4 |
| 10 | GCLK_EVSYS_CHANNEL_5 | EVSYS_CHANNEL_5 |
| 11 | GCLK_EVSYS_CHANNEL_6 | EVSYS_CHANNEL_6 |
| 12 | GCLK_EVSYS_CHANNEL_7 | EVSYS_CHANNEL_7 |
| 13 | GCLK_EVSYS_CHANNEL_8 | EVSYS_CHANNEL_8 |
| 14 | GCLK_EVSYS_CHANNEL_9 | EVSYS_CHANNEL_9 |
| 15 | GCLK_EVSYS_CHANNEL_10 | EVSYS_CHANNEL_10 |
| 16 | GCLK_EVSYS_CHANNEL_11 | EVSYS_CHANNEL_11 |
| 17 | GCLK_SERCOM[0,1,2,3,4]_SLOW | SERCOM[0,1,2,3,4]_SLOW |
| 18 | GCLK_SERCOM0_CORE | SERCOM0_CORE |
| 19 | GCLK_SERCOM1_CORE | SERCOM1_CORE |
| 20 | GCLK_SERCOM2_CORE | SERCOM2_CORE |
| 21 | GCLK_SERCOM3_CORE | SERCOM3_CORE |
| 22 | GCLK_SERCOM4_CORE | SERCOM4_CORE |
| 23 | GCLK_SERCOM5_SLOW | SERCOM5_SLOW |
| 24 | GCLK_SERCOM5_CORE | SERCOM5_CORE |
| 25 | GCLK_TCC0, GCLK_TCC1 | TCC0,TCC1 |
| 26 | GCLK_TCC2 | TCC2 |
| 27 | GCLK_TC0, GCLK_TC1 | TC0,TC1 |
| 28 | GCLK_TC2, GCLK_TC3 | TC2,TC3 |
| 29 | GCLK_TC4 | TC4 |
| 30 | GCLK_ADC | ADC |
| 31 | GCLK_AC | AC |
| 32 | GCLK_DAC | DAC |
| 33 | GCLK_PTC | PTC |
| 34 | GCLK_CCL | CCL |