11.2 Physical Memory Map

The high-speed bus is implemented as a bus matrix. All high-speed bus addresses are fixed, and they are never remapped in any way, even during boot. The 32-bit physical address space is mapped as follows:

Table 11-1. SAM L21 Physical Memory Map⁽¹⁾
Memory	Start address	Size [KB]
Memory	Start address	SAML21x18	SAML21x17	SAML21x16	SAML21E15
Embedded Flash	0x00000000	256	128	64	32
Embedded RWW section	0x00400000	8	4	2	1
Embedded SRAM	0x20000000	32	16	8	4
Embedded low-power SRAM	0x30000000	8	8	4	2
Peripheral Bridge A	0x40000000	64	64	64	64
Peripheral Bridge B	0x41000000	64	64	64	64
Peripheral Bridge C	0x42000000	64	64	64	64
Peripheral Bridge D	0x43000000	64	64	64	64
Peripheral Bridge E	0x44000000	64	64	64	64
IOBUS	0x60000000	0.5	0.5	0.5	0.5

Note: 1. x = G, J, or E.

Table 11-2. Flash Memory Parameters⁽¹⁾
Device	Flash size [KB]	Number of pages	Page size [Bytes]
SAML21x18	256	4096	64
SAML21x17	128	2048	64
SAML21x16	64	1024	64
SAML21E15	32	512	64

Note: 1. x = G, J, or E.

Table 11-3. RWW Section Parameters⁽¹⁾
Device	Flash size [KB]	Number of pages	Page size [Bytes]
SAML21x18	8	128	64
SAML21x17	4	64	64
SAML21x16	2	32	64
SAML21E15	1	16	64

Note: 1. x = G, J, or E.

SAM L21

11.2 Physical Memory Map