36.8.17 Period Value

Name: PER
Offset: 0x40
Reset: 0xFFFFFFFF
Property: Write-Synchronized

Bit 3130292827262524 
 PER[25:18] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 
Bit 2322212019181716 
 PER[17:10] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 
Bit 15141312111098 
 PER[9:2] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 
Bit 76543210 
 PER[1:0]DITHER[5:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 

Bits 31:6 – PER[25:0] Period Value

These bits hold the value of the period register.

Note: When the TCC is configured as 16- or 24-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register. m is dependent on the Resolution bit in the Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTIONBits [31:m]
0x0 - NONE31:0
0x1 - DITH431:4
0x2 - DITH531:5
0x3 - DITH631:6 (depicted)

Bits 5:0 – DITHER[5:0] Dithering Cycle Number

These bits hold the number of extra cycles that are added on the PWM pulse period every 64 PWM frames.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTIONBits [n:0]
0x0 - NONE-
0x1 - DITH43:0
0x2 - DITH54:0
0x3 - DITH65:0 (depicted)