36.8.17 Period Value
| Name: | PER |
| Offset: | 0x40 |
| Reset: | 0xFFFFFFFF |
| Property: | Write-Synchronized |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PER[25:18] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PER[17:10] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PER[9:2] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PER[1:0] | DITHER[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bits 31:6 – PER[25:0] Period Value
These bits hold the value of the period register.
Note: When the TCC is configured as 16-
or 24-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of
the register. m is dependent on the Resolution bit in the Control A register
(CTRLA.RESOLUTION):
| CTRLA.RESOLUTION | Bits [31:m] |
|---|---|
| 0x0 - NONE | 31:0 |
| 0x1 - DITH4 | 31:4 |
| 0x2 - DITH5 | 31:5 |
| 0x3 - DITH6 | 31:6 (depicted) |
Bits 5:0 – DITHER[5:0] Dithering Cycle Number
Note: This bit field consists of the n LSB
of the register. n is dependent on the value of the Resolution bits in the Control A
register (CTRLA.RESOLUTION):
| CTRLA.RESOLUTION | Bits [n:0] |
|---|---|
| 0x0 - NONE | - |
| 0x1 - DITH4 | 3:0 |
| 0x2 - DITH5 | 4:0 |
| 0x3 - DITH6 | 5:0 (depicted) |