26.8.2 CRC Control

Name: CRCCTRL
Offset: 0x02
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected

Bit 15141312111098 
   CRCSRC[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 76543210 
     CRCPOLY[1:0]CRCBEATSIZE[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 13:8 – CRCSRC[5:0] CRC Input Source

These bits select the input source for generating the CRC, as shown in the table below. The selected source is locked until either the CRC generation is completed or the CRC module is disabled. This means the CRCSRC cannot be modified when the CRC operation is ongoing. The lock is signaled by the CRCBUSY status bit. CRC generation complete is generated and signaled from the selected source when used with the DMA channel.

ValueNameDescription
0x00 NOACT No action
0x01 IO I/O interface
0x02-0x1F - Reserved
0x20 CHN DMA channel 0
0x21 CHN DMA channel 1
0x22 CHN DMA channel 2
0x23 CHN DMA channel 3
0x24 CHN DMA channel 4
0x25 CHN DMA channel 5
0x26 CHN DMA channel 6
0x27 CHN DMA channel 7
0x28 CHN DMA channel 8
0x29 CHN DMA channel 9
0x2A CHN DMA channel 10
0x2B CHN DMA channel 11
0x2C CHN DMA channel 12
0x2D CHN DMA channel 13
0x2E CHN DMA channel 14
0x2F CHN DMA channel 15

Bits 3:2 – CRCPOLY[1:0] CRC Polynomial Type

These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface, as shown in the table below.

ValueNameDescription
0x0 CRC16 CRC-16 (CRC-CCITT)
0x1 CRC32 CRC32 (IEEE 802.3)
0x2-0x3 Reserved

Bits 1:0 – CRCBEATSIZE[1:0] CRC Beat Size

These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface.

ValueNameDescription
0x0 BYTE 8-bit bus transfer
0x1 HWORD 16-bit bus transfer
0x2 WORD 32-bit bus transfer
0x3 Reserved