36.6.2.5 Compare Operations
By default, the Compare/Capture channel is configured for compare operations. To perform capture operations, it must be re-configured.
When using the TCC with the Compare/Capture Value registers (CCx) for compare operations, the counter value is continuously compared to the values in the CCx registers. This can be used for timer or for waveform operation.
The Channel x Compare/Capture Buffer Value (CCBUFx) registers provide double buffer capability. The double buffering synchronizes the update of the CCx register with the buffer value at the UPDATE condition or a force update command (CTRLBSET.CMD=0x3, UPDATE). For further details, refer to Double Buffering. The synchronization prevents the occurrence of odd-length, non-symmetrical pulses and ensures glitch-free output.
Waveform Output Generation Operations
- Choose a waveform generation mode in the Waveform Generation Operation bit in Waveform register (WAVE.WAVEGEN).
- Optionally invert the waveform output WO[x] by writing the corresponding Waveform Output x Inversion bit in the Driver Control register (DRVCTRL.INVENx).
- Configure the pins with the I/O Pin Controller. Refer to PORT - I/O Pin Controller for details.
The counter value is continuously compared with each CCx value. On a comparison match, the Match or Capture Channel x bit in the Interrupt Flag Status and Clear register (INTFLAG.MCx) will be set on the next zero-to-one transition of CLK_TCC_COUNT (see Normal Frequency Operation). An interrupt and/or event can be generated on the same condition if Match/Capture occurs, i.e. INTENSET.MCx and/or EVCTRL.MCEOx is '1'. Both interrupt and event can be generated simultaneously. The same condition generates a DMA request.
- Normal Frequency (NFRQ)
- Match Frequency (MFRQ)
- Normal Pulse-Width Modulation (NPWM)
- Dual-slope, interrupt/event at TOP (DSTOP)
- Dual-slope, interrupt/event at ZERO (DSBOTTOM)
- Dual-slope, interrupt/event at Top and ZERO (DSBOTH)
- Dual-slope, critical interrupt/event at ZERO (DSCRITICAL)
When using MFRQ configuration, the TOP value is defined by the CC0 register value. For the other waveform operations, the TOP value is defined by the Period (PER) register value.
For dual-slope waveform operations, the update time occurs when the counter reaches ZERO. For the other waveforms generation modes, the update time occurs on counter wraparound, on overflow, underflow, or re-trigger.
The table below shows the update counter and overflow event/interrupt generation conditions in different operation modes.
Name | Operation | TOP | Update | Output Waveform | OVFIF/Event | ||
---|---|---|---|---|---|---|---|
On Match | On Update | Up | Down | ||||
NFRQ | Normal Frequency | PER | TOP/ ZERO | Toggle | Stable | TOP | ZERO |
MFRQ | Match Frequency | CC0 | TOP/ ZERO | Toggle | Stable | TOP | ZERO |
NPWM | Single-slope PWM | PER | TOP/ ZERO | See section 'Output Polarity' below | TOP | ZERO | |
DSCRITICAL | Dual-slope PWM | PER | ZERO | - | ZERO | ||
DSBOTTOM | Dual-slope PWM | PER | ZERO | - | ZERO | ||
DSBOTH | Dual-slope PWM | PER | TOP(1) & ZERO | TOP | ZERO | ||
DSTOP | Dual-slope PWM | PER | ZERO | TOP | – |
- The UPDATE condition on TOP only will occur when circular buffer is enabled for the channel.
Normal Frequency (NFRQ)
For Normal Frequency generation, the period time (T) is controlled by the period register (PER). The waveform generation output (WO[x]) is toggled on each compare match between COUNT and CCx, and the corresponding Match or Capture Channel x Interrupt Flag (EVCTRL.MCEOx) will be set.
Match Frequency (MFRQ)
For Match Frequency generation, the period time (T) is controlled by CC0 register instead of PER. WO[0] toggles on each update condition.
Normal Pulse-Width Modulation (NPWM)
NPWM uses single-slope PWM generation.
Single-Slope PWM Operation
For single-slope PWM generation, the period time (T) is controlled by Top value, and CCx controls the duty cycle of the generated waveform output. When up-counting, the WO[x] is set at start or compare match between the COUNT and TOP values, and cleared on compare match between COUNT and CCx register values. When down-counting, the WO[x] is cleared at start or compare match between the COUNT and ZERO values, and set on compare match between COUNT and CCx register values.
The following equation calculates the exact resolution for a single-slope PWM (RPWM_SS) waveform:
The PWM frequency depends on the Period register value (PER) and the peripheral clock frequency (fGCLK_TCC), and can be calculated by the following equation:
Where N represents the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024).
Dual-Slope PWM Generation
For dual-slope PWM generation, the period setting (TOP) is controlled by PER, while CCx control the duty cycle of the generated waveform output. The figure below shows how the counter repeatedly counts from ZERO to PER and then from PER to ZERO. The waveform generator output is set on compare match when up-counting, and cleared on compare match when down-counting. An interrupt/event is generated on TOP and/or ZERO, depend of Dual slope.
In DSBOTH operation, a second update time occurs on TOP when circular buffer is enabled.
Using dual-slope PWM results in a lower maximum operation frequency compared to single-slope PWM generation. The period (TOP) defines the PWM resolution. The minimum resolution is 1 bit (TOP=0x00000001).
The following equation calculates the exact resolution for dual-slope PWM (RPWM_DS):
The PWM frequency fPWM_DS depends on the period setting (TOP) and the peripheral clock frequency fGCLK_TCC, and can be calculated by the following equation:
N represents the prescaler divider used. The waveform generated will have a maximum frequency of half of the TCC clock frequency (fGCLK_TCC) when TOP is set to 0x00000001 and no prescaling is used.
The pulse width (PPWM_DS) depends on the compare channel (CCx) register value and the peripheral clock frequency (fGCLK_TCC), and can be calculated by the following equation:
N represents the prescaler divider used.
Dual-Slope Critical PWM Generation
Critical mode generation allows generation of non-aligned centered pulses. In this mode, the period time is controlled by PER while CCx control the generated waveform output edge during up-counting and CC(x+CC_NUM/2) control the generated waveform output edge during down-counting.
Output Polarity
The polarity (WAVE.POLx) is available in all waveform output generation. In single-slope and dual-slope PWM operation, it is possible to invert the pulse edge alignment individually on start or end of a PWM cycle for each compare channels. The table below shows the waveform output set/clear conditions, depending on the settings of timer/counter, direction, and polarity.
Waveform Generation operation | DIR | POLx | Waveform Generation Output Update | |
---|---|---|---|---|
Set | Clear | |||
Single-Slope PWM | 0 | 0 | Timer/counter matches TOP | Timer/counter matches CCx |
1 | Timer/counter matches CC | Timer/counter matches TOP | ||
1 | 0 | Timer/counter matches CC | Timer/counter matches ZERO | |
1 | Timer/counter matches ZERO | Timer/counter matches CC | ||
Dual-Slope PWM | x | 0 | Timer/counter matches CC when counting up | Timer/counter matches CC when counting down |
1 | Timer/counter matches CC when counting down | Timer/counter matches CC when counting up |
In Normal and Match Frequency, the WAVE.POLx value represents the initial state of the waveform output.