21.8.4 Status
| Name: | STATUS |
| Offset: | 0x0C |
| Reset: | 0x00000100 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DPLLLDRTO | DPLLLTO | DPLLLCKF | DPLLLCKR | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DFLLRCS | DFLLLCKC | DFLLLCKF | DFLLOOB | DFLLRDY | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OSC16MRDY | XOSCRDY | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Bit 19 – DPLLLDRTO DPLL Loop Divider Ratio Update Complete
| Value | Description |
|---|---|
| 0 | DPLL Loop Divider Ratio Update Complete not detected. |
| 1 | DPLL Loop Divider Ratio Update Complete detected. |
Bit 18 – DPLLLTO DPLL Lock Timeout
| Value | Description |
|---|---|
| 0 | DPLL Lock time-out not detected. |
| 1 | DPLL Lock time-out detected. |
Bit 17 – DPLLLCKF DPLL Lock Fall
| Value | Description |
|---|---|
| 0 | DPLL Lock fall edge not detected. |
| 1 | DPLL Lock fall edge detected. |
Bit 16 – DPLLLCKR DPLL Lock Rise
| Value | Description |
|---|---|
| 0 | DPLL Lock rise edge not detected. |
| 1 | DPLL Lock fall edge detected. |
Bit 12 – DFLLRCS DFLL Reference Clock Stopped
| Value | Description |
|---|---|
| 0 | DFLL reference clock is running. |
| 1 | DFLL reference clock has stopped. |
Bit 11 – DFLLLCKC DFLL Lock Coarse
| Value | Description |
|---|---|
| 0 | No DFLL coarse lock detected. |
| 1 | DFLL coarse lock detected. |
Bit 10 – DFLLLCKF DFLL Lock Fine
| Value | Description |
|---|---|
| 0 | No DFLL fine lock detected. |
| 1 | DFLL fine lock detected. |
Bit 9 – DFLLOOB DFLL Out Of Bounds
| Value | Description |
|---|---|
| 0 | No DFLL Out Of Bounds detected. |
| 1 | DFLL Out Of Bounds detected. |
Bit 8 – DFLLRDY DFLL Ready
| Value | Description |
|---|---|
| 0 | DFLL registers update is ongoing. Registers update is requested through DFLLSYNC.READREQ, or after a write access in DFLLCTRL, DFLLVAL or DFLLMUL register. |
| 1 | DFLL registers are stable and ready for read/write access. |
Bit 4 – OSC16MRDY OSC16M Ready
| Value | Description |
|---|---|
| 0 | OSC16M is not ready. |
| 1 | OSC16M is stable and ready to be used as a clock source. |
Bit 0 – XOSCRDY XOSC Ready
| Value | Description |
|---|---|
| 0 | XOSC is not ready. |
| 1 | XOSC is stable and ready to be used as a clock source. |