21.8.4 Status

Name: STATUS
Offset: 0x0C
Reset: 0x00000100
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     DPLLLDRTODPLLLTODPLLLCKFDPLLLCKR 
Access RRRR 
Reset 0000 
Bit 15141312111098 
    DFLLRCSDFLLLCKCDFLLLCKFDFLLOOBDFLLRDY 
Access RRRRR 
Reset 00001 
Bit 76543210 
    OSC16MRDY   XOSCRDY 
Access RR 
Reset 00 

Bit 19 – DPLLLDRTO DPLL Loop Divider Ratio Update Complete

ValueDescription
0 DPLL Loop Divider Ratio Update Complete not detected.
1 DPLL Loop Divider Ratio Update Complete detected.

Bit 18 – DPLLLTO DPLL Lock Timeout

ValueDescription
0 DPLL Lock time-out not detected.
1 DPLL Lock time-out detected.

Bit 17 – DPLLLCKF DPLL Lock Fall

ValueDescription
0 DPLL Lock fall edge not detected.
1 DPLL Lock fall edge detected.

Bit 16 – DPLLLCKR DPLL Lock Rise

ValueDescription
0 DPLL Lock rise edge not detected.
1 DPLL Lock fall edge detected.

Bit 12 – DFLLRCS DFLL Reference Clock Stopped

ValueDescription
0 DFLL reference clock is running.
1 DFLL reference clock has stopped.

Bit 11 – DFLLLCKC DFLL Lock Coarse

ValueDescription
0 No DFLL coarse lock detected.
1 DFLL coarse lock detected.

Bit 10 – DFLLLCKF DFLL Lock Fine

ValueDescription
0 No DFLL fine lock detected.
1 DFLL fine lock detected.

Bit 9 – DFLLOOB DFLL Out Of Bounds

ValueDescription
0 No DFLL Out Of Bounds detected.
1 DFLL Out Of Bounds detected.

Bit 8 – DFLLRDY DFLL Ready

ValueDescription
0 DFLL registers update is ongoing. Registers update is requested through DFLLSYNC.READREQ, or after a write access in DFLLCTRL, DFLLVAL or DFLLMUL register.
1 DFLL registers are stable and ready for read/write access.

Bit 4 – OSC16MRDY OSC16M Ready

ValueDescription
0 OSC16M is not ready.
1 OSC16M is stable and ready to be used as a clock source.

Bit 0 – XOSCRDY XOSC Ready

ValueDescription
0 XOSC is not ready.
1 XOSC is stable and ready to be used as a clock source.