15.7 Chip Erase

Chip-Erase consists of removing all sensitive information stored in the chip and clearing the NVMCTRL security bit. Therefore, all volatile memories and the Flash memory (including the EEPROM emulation area) will be erased. The Flash auxiliary rows, including the user row, will not be erased.

When the device is protected, the debugger must first reset the device in order to be detected. This ensures that internal registers are reset after the protected state is removed. The Chip-Erase operation is triggered by writing a '1' to the Chip-Erase bit in the Control register (CTRL.CE). This command will be discarded if the DSU is protected by the Peripheral Access Controller (PAC). Once issued, the module clears volatile memories prior to erasing the Flash array. To ensure that the Chip-Erase operation is completed, check the Done bit of the Status A register (STATUSA.DONE).

The Chip-Erase operation depends on clocks and power management features that can be altered by the CPU. For that reason, it is recommended to issue a Chip- Erase after a Cold-Plugging procedure to ensure that the device is in a known and safe state.

The recommended sequence is as follows:
  1. Issue the Cold-Plugging procedure (refer to Cold Plugging). The device then:
    1. Detects the debugger probe.
    2. Holds the CPU in reset.
  2. Issue the Chip-Erase command by writing a '1' to CTRL.CE. The device then:
    1. Clears the system volatile memories.
    2. Erases the whole Flash array (including the EEPROM emulation area, not including auxiliary rows).
    3. Erases the lock row, removing the NVMCTRL security bit protection.
  3. Check for completion by polling STATUSA.DONE (read as '1' when completed).
  4. Reset the device to let the NVMCTRL update the fuses.