38.5.3 Clocks
The AES bus clock (CLK_AES_APB) can be enabled and disabled in the MCLK – Main Clock, and the default state of CLK_AES_APB can be found in Peripheral Clock Masking. The module is fully clocked by CLK_AES_APB.
The AES bus clock (CLK_AES_APB) can be enabled and disabled in the MCLK – Main Clock, and the default state of CLK_AES_APB can be found in Peripheral Clock Masking. The module is fully clocked by CLK_AES_APB.
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