12.4.3 Configuration

Figure 12-2. Master-Slave Relations High-Speed Bus Matrix
Figure 12-3. Master-Slave Relations Low-Power Bus Matrix
Table 12-4. High-Speed Bus Matrix Masters
High-Speed Bus Matrix MastersMaster ID
CM0+ - Cortex M0+ Processor0
DSU - Device Service Unit1
L2HBRIDGEM - Low-Power to High-Speed bus matrix AHB to AHB bridge2
Table 12-5. High-Speed Bus Matrix Slaves
High-Speed Bus Matrix SlavesSlave ID
Internal Flash Memory0
HS SRAM Port 0 - CM0+ Access1
HS SRAM Port 1 - DSU Access2
AHB-APB Bridge B3
H2LBRIDGES - High-Speed to Low-Power bus matrix AHB to AHB bridge4
Table 12-6. Low-Power Bus Matrix Masters
Low-Power Bus Matrix MastersMaster ID
H2LBRIDGEM - High-Speed to Low-Power bus matrix AHB to AHB bridge0
DMAC - Direct Memory Access Controller - Data Access2
Table 12-7. Low-Power Bus Matrix Slaves
Low-Power Bus Matrix SlavesSlave ID
AHB-APB Bridge A0
AHB-APB Bridge C1
AHB-APB Bridge D2
AHB-APB Bridge E3
LP SRAM Port 2- H2LBRIDGEM access5
LP SRAM Port 1- DMAC access7
L2HBRIDGES - Low-Power to High-Speed bus matrix AHB to AHB bridge8
HS SRAM Port 2- HMATRIXLP access9