26.10.1 Block Transfer Control

The BTCTRL register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Name: BTCTRL
Offset: 0x00
Reset: 0
Property: -

Bit 15141312111098 
 STEPSIZE[2:0]STEPSELDSTINCSRCINCBEATSIZE[1:0] 
Access -------- 
Reset 00000000 
Bit 76543210 
    BLOCKACT[1:0]EVOSEL[1:0]VALID 
Access ----- 
Reset 00000 

Bits 15:13 – STEPSIZE[2:0] Address Increment Step Size

These bits select the address increment step size. The setting apply to source or destination address, depending on STEPSEL setting.

ValueNameDescription
0x0X1Next ADDR = ADDR + (Beat size in byte) * 1
0x1X2Next ADDR = ADDR + (Beat size in byte) * 2
0x2X4Next ADDR = ADDR + (Beat size in byte) * 4
0x3X8Next ADDR = ADDR + (Beat size in byte) * 8
0x4X16Next ADDR = ADDR + (Beat size in byte) * 16
0x5X32Next ADDR = ADDR + (Beat size in byte) * 32
0x6X64Next ADDR = ADDR + (Beat size in byte) * 64
0x7X128Next ADDR = ADDR + (Beat size in byte) * 128

Bit 12 – STEPSEL Step Selection

This bit selects if source or destination addresses are using the step size settings.

ValueNameDescription
0x0DSTStep size settings apply to the destination address
0x1SRCStep size settings apply to the source address

Bit 11 – DSTINC Destination Address Increment Enable

Writing a '0' to this bit will disable the destination address incrementation. The address will be kept fixed during the data transfer.

Writing a '1' to this bit will enable the destination address incrementation. By default, the destination address is incremented by 1. If the STEPSEL bit is cleared, flexible step-size settings are available in the STEPSIZE register.

ValueDescription
0The Destination Address Increment is disabled.
1The Destination Address Increment is enabled.

Bit 10 – SRCINC Source Address Increment Enable

Writing a '0' to this bit will disable the source address incrementation. The address will be kept fixed during the data transfer.

Writing a '1' to this bit will enable the source address incrementation. By default, the source address is incremented by 1. If the STEPSEL bit is set, flexible step-size settings are available in the STEPSIZE register.

ValueDescription
0The Source Address Increment is disabled.
1The Source Address Increment is enabled.

Bits 9:8 – BEATSIZE[1:0] Beat Size

These bits define the size of one beat. A beat is the size of one data transfer bus access, and the setting apply to both read and write accesses.

ValueNameDescription
0x0BYTE8-bit bus transfer
0x1HWORD16-bit bus transfer
0x2WORD32-bit bus transfer
otherReserved

Bits 4:3 – BLOCKACT[1:0] Block Action

These bits define what actions the DMAC should take after a block transfer has completed.

BLOCKACT[1:0]NameDescription
0x0NOACTChannel will be disabled if it is the last block transfer in the transaction
0x1INTChannel will be disabled if it is the last block transfer in the transaction and block interrupt
0x2SUSPENDChannel suspend operation is completed
0x3BOTHBoth channel suspend operation and block interrupt

Bits 2:1 – EVOSEL[1:0] Event Output Selection

These bits define the event output selection.

EVOSEL[1:0]NameDescription
0x0DISABLEEvent generation disabled
0x1BLOCKEvent strobe when block transfer complete
0x2Reserved
0x3BEATEvent strobe when beat transfer complete

Bit 0 – VALID Descriptor Valid

Writing a '0' to this bit in the Descriptor or Write-Back memory will suspend the DMA channel operation when fetching the corresponding descriptor.

The bit is automatically cleared in the Write-Back memory section when channel is aborted, when an error is detected during the block transfer, or when the block transfer is completed.

ValueDescription
0The descriptor is not valid.
1The descriptor is valid.