25.10.4 Interrupt Enable Set in COUNT16 mode (CTRLA.MODE=1)

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x0A
Reset: 0x0000
Property: PAC Write-Protection

Bit 15141312111098 
 OVF     CMP1CMP0 
Access R/WR/WR/W 
Reset 000 
Bit 76543210 
 PER7PER6PER5PER4PER3PER2PER1PER0 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 15 – OVF Overflow Interrupt Enable

Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt.
ValueDescription
0 The Overflow interrupt is disabled.
1 The Overflow interrupt is enabled.

Bits 8, 9 – CMPn Compare n Interrupt Enable [n = 1..0]

Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Compare n Interrupt Enable bit, which disables the Compare n interrupt.
ValueDescription
0 The Compare n interrupt is disabled.
1 The Compare n interrupt is enabled.

Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 7..0]

Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable bit, which enables the Periodic Interval n interrupt.
ValueDescription
0 Periodic Interval n interrupt is disabled.
1 Periodic Interval n interrupt is enabled.