1.5.3 Block Design Methodology: Propagate Chip-Level Hardwired Connections to the Top Module
(Ask a Question)Libero SoC v2025.1 adds support to propagate chip-level hardwired connections (for example, OSC_RC50MHZ, CCC to DELCAL) to the top module in block mode for SmartFusion2, IGLOO2, and RTG4 devices. This support resolves previous compile and layout issues specific to block design methodology.