4.1.1 Communication Interface and Protocol

The ICSP/Enhanced ICSP interface is a two-wire SPI, implemented using the PGECx and PGEDx pins. The PGECx pin is used as a clock input pin, and the clock source must be provided by the programmer. The PGEDx pin is used for sending command data to and receiving response data from the PE.

Note: For Enhanced ICSP, all serial data are transmitted on the falling edge of PGECx and latched on the rising edge of PGECx. All data transmissions are sent with the MSb first using 16-bit mode (see Figure 4-1).

Figure 4-1. Programming Executive Serial Timing

Since a two-wire SPI is used, and data transmissions are bidirectional, a simple protocol is used to control the direction of PGEDx. When the programmer completes a command transmission, it releases the PGEDx line and allows the PE to drive this line high. The PE keeps the PGEDx line high to indicate that it is processing the command.

After the PE has processed the command, it brings PGEDx low (P9B) to indicate to the programmer that the response is available to be clocked out. The programmer can begin to clock out the response after a maximum wait (P9B), and the programmer must provide the necessary amount of clock pulses to receive the entire response from the PE.

After the entire response is clocked out, the programmer should terminate the clock on PGECx until it is time to send another command to the Programming Executive. This protocol is shown in Figure 4-2.

Figure 4-2. Programming Executive – Programmer Communication Protocol