1.5 Memory Map

The program memory map extends from 0x000000 to 0xFFFFFE. User program code storage is located at the base of the memory map. The last row (128 instruction words) of the last page of implemented program memory is reserved for the device Configuration bits. Caution should be used when placing code in the last page of user memory. When programming the device configuration, the whole last page must first be erased, including any code located in the last page.

Table 1-2 lists the user memory address limit and the available number of instruction words (including the device configuration area), the number of write blocks and the number of erase blocks present in each device variant.

Table 1-2. Flash Code Memory Size
Device FamilyUser Memory Limit (Instruction Words)Write Blocks/ No. of RowsErase Blocks/No. of Pages

dsPIC33CK256MC00X

0x02BFFE (90112)

704

88

dsPIC33CK128MC00X

0X015FFE (45056)

352

44

dsPIC33CK64MC00X0x00AFFE (22528)17622
dsPIC33CK32MC00X0x005FFE (12288)9612

Locations 0x800000 through 0x800FFE are reserved for executive code memory. This region stores the PE and the debugging executive, which are used for device programming. This region of memory cannot be used to store user code. See The Programming Executive for more information.

Locations 0xFF0000 and 0xFF0002 are reserved for the Device ID Word registers. These bits can be used by the programmer to identify which device type is being programmed. They are described in Device ID/Unique ID. The Device ID registers read out normally, even after code protection is applied.

The locations, 0x801700 to 0x8017FE, are a One-Time-Programmable (OTP) memory area. The user OTP words can be used for storing product information, such as serial numbers, system manufacturing dates, manufacturing lot numbers and other application-specific information. They are described in User One-Time-Programmable (OTP) Memory.

Figure 1-7 through Figure 1-11 show generic memory maps for the devices listed in Table 1-2. See the “Memory Organization” chapter in the specific device data sheet for exact memory addresses.

Table 1-3. Device Row and Page Size
Instruction Words (24 bits)

Row

128

Page

1024

Figure 1-7. Program Memory Map for dsPIC33CKXXXMC00X(1)
Note:
  1. Memory areas are not shown to scale.
  2. Calibration data area must be maintained during programming.
  3. Calibration data area includes the UDID register location.
Figure 1-8. Program Memory Map for dsPIC33CK256MC00X(1)
Figure 1-9. Program Memory Map for dsPIC33CK128MC00X(1)
Figure 1-10. Program Memory Map for dsPIC33CK64MC00X(1)
Figure 1-11. Program Memory Map for dsPIC33CK32MC00X(1)