49.7.7.7 Multiple Data Mode

Multiple Data mode minimizes the number of accesses by concatenating the data to send/read in one access.

When SPI_FMR.TXRDYM > 0, the Transmit FIFO operates in Multiple Data mode.

When SPI_FMR.RXRDYM > 0, the Receive FIFO operates in Multiple Data mode.

Multiple data can be read from the Receive FIFO only in Client mode (SPI_MR.MSTR=0).

The Transmit FIFO can be loaded with multiple data in the same access by configuring TXRDYM>0 and when SPI_MR.PS=0.

In Multiple Data mode, up to two data can be written in one SPI_TDR write access. It is also possible to read up to four data in one SPI_RDR access if SPI_CSRx.BITS is configured to ‘0’ (8-bit data size) and up to two data if SPI_CSRx.BITS is configured to a value other than ‘0’ (more than 8-bit data size).

The number of data to write/read is defined by the size of the register access. If the access is a byte-size register access, only one data is written/read. If the access is a halfword size register access, then up to two data are read and only one data is written. Lastly, if the access is a word-size register access, then up to four data are read and up to two data are written.

Written/read data are always right-aligned, as described in sections SPI Receive Data Register (FIFO Multiple Data, 8-bit), SPI Receive Data Register (FIFO Mutliple Data, 16-bit) and SPI Transmit Data Register (FIFO Multiple Data, 8 to 16-bit).

As an example, if the Transmit FIFO is empty and there are six data to send, either of the following write accesses may be performed:

six SPI_TDR-byte write accesses
three SPI_TDR-halfword write accesses

With a Receive FIFO containing six data, any of the following read accesses may be performed:

six SPI_RDR-byte read accesses
three SPI_RDR-halfword read accesses
one SPI_RDR-word read access and one SPI_RDR-halfword read access