41.7.4 UDPHS Interrupt Status Register
| Name: | UDPHS_INTSTA |
| Offset: | 0x14 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DMA_7 | DMA_6 | DMA_5 | DMA_4 | DMA_3 | DMA_2 | DMA_1 | |||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| EPT_15 | EPT_14 | EPT_13 | EPT_12 | EPT_11 | EPT_10 | EPT_9 | EPT_8 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EPT_7 | EPT_6 | EPT_5 | EPT_4 | EPT_3 | EPT_2 | EPT_1 | EPT_0 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UPSTR_RES | ENDOFRSM | WAKE_UP | ENDRESET | INT_SOF | MICRO_SOF | DET_SUSPD | SPEED | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 25, 26, 27, 28, 29, 30, 31 – DMA_x DMA Channel x Interrupt
| Value | Description |
|---|---|
| 0 | Reset when the UDPHS_DMASTATUSx interrupt source is cleared. |
| 1 | Set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the DMA_x bit in UDPHS_IEN. |
Bits 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – EPT_x Endpoint x Interrupt (cleared upon USB reset)
| Value | Description |
|---|---|
| 0 | Reset when the UDPHS_EPTSTAx interrupt source is cleared. |
| 1 | Set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the EPT_x bit in UDPHS_IEN. |
Bit 7 – UPSTR_RES Upstream Resume Interrupt
| Value | Description |
|---|---|
| 0 | Cleared by setting the UPSTR_RES bit in UDPHS_CLRINT. |
| 1 | Set by hardware when the UDPHS controller is sending a resume signal called “upstream resume”. This triggers a UDPHS interrupt when the UPSTR_RES bit is set in UDPHS_IEN. |
Bit 6 – ENDOFRSM End Of Resume Interrupt
| Value | Description |
|---|---|
| 0 | Cleared by setting the ENDOFRSM bit in UDPHS_CLRINT. |
| 1 | Set by hardware when the UDPHS controller detects a good end of resume signal initiated by the host. This triggers a UDPHS interrupt when the ENDOFRSM bit is set in UDPHS_IEN. |
Bit 5 – WAKE_UP Wake Up CPU Interrupt
| Value | Description |
|---|---|
| 0 | Cleared by setting the WAKE_UP bit in UDPHS_CLRINT. |
| 1 | Set by
hardware when the UDPHS controller is in SUSPEND state and is re-activated by a
filtered non-idle signal from the UDPHS line (not by an upstream resume). This
triggers a UDPHS interrupt when the WAKE_UP bit is set in UDPHS_IEN register. When
receiving this interrupt, the user has to enable the device controller clock prior
to operation. Note: this interrupt
is generated even if the device controller clock is
disabled. |
Bit 4 – ENDRESET End Of Reset Interrupt
| Value | Description |
|---|---|
| 0 | Cleared by setting the ENDRESET bit in UDPHS_CLRINT. |
| 1 | Set by hardware when an End Of Reset has been detected by the UDPHS controller. This triggers a UDPHS interrupt when the ENDRESET bit is set in UDPHS_IEN. |
Bit 3 – INT_SOF Start Of Frame Interrupt
Note: The Micro Start Of Frame Interrupt (MICRO_SOF), and the Start Of Frame Interrupt
(INT_SOF) are not generated at the same time.
| Value | Description |
|---|---|
| 0 | Cleared by setting the INT_SOF bit in UDPHS_CLRINT. |
| 1 | Set by hardware when an UDPHS Start Of Frame PID (SOF) has been detected (every 1 ms) or synthesized by UDPHS. This triggers a UDPHS interrupt when the INT_SOF bit is set in UDPHS_IEN register. In case of detected SOF, in High Speed mode, the MICRO_FRAME_NUMBER field is cleared in UDPHS_FNUM register and the FRAME_NUMBER field is updated. |
Bit 2 – MICRO_SOF Micro Start Of Frame Interrupt
Note: The Micro Start Of Frame Interrupt (MICRO_SOF), and the Start Of Frame Interrupt
(INT_SOF) are not generated at the same time.
| Value | Description |
|---|---|
| 0 | Cleared by setting the MICRO_SOF bit in UDPHS_CLRINT register. |
| 1 | Set by hardware when an UDPHS micro start of frame PID (SOF) has been detected (every 125 us) or synthesized by UDPHS. This triggers a UDPHS interrupt when the MICRO_SOF bit is set in UDPHS_IEN. In case of detected SOF, the MICRO_FRAME_NUM field in UDPHS_FNUM register is incremented and the FRAME_NUMBER field does not change. |
Bit 1 – DET_SUSPD Suspend Interrupt
| Value | Description |
|---|---|
| 0 | Cleared by setting the DET_SUSPD bit in UDPHS_CLRINT register. |
| 1 | Set by hardware when a UDPHS Suspend (Idle bus for three frame periods, a J state for 3 ms) is detected. This triggers a UDPHS interrupt when the DET_SUSPD bit is set in UDPHS_IEN register. |
Bit 0 – SPEED Speed Status
| Value | Description |
|---|---|
| 0 | Reset by hardware when the hardware is in Full Speed mode. |
| 1 | Set by hardware when the hardware is in High Speed mode. |