41.7.12 UDPHS Endpoint Control Disable Register (Isochronous Endpoint)

This register view is relevant only if UDPHS_EPTCFGx.EPT_TYPE = 0x1.

For additional information, see UDPHS_EPTCTLx.

Name: UDPHS_EPTCTLDISx
Offset: 0x0108 + x*0x20 [x=0..15]
Reset: 
Property: Write-only

Bit 3130292827262524 
 SHRT_PCKT        
Access W 
Reset  
Bit 2322212019181716 
      BUSY_BANK   
Access W 
Reset  
Bit 15141312111098 
  ERR_FLUSHERR_CRC_NTRERR_FL_ISOTXRDY_TRERTX_COMPLTRXRDY_TXKLERR_OVFLW 
Access WWWWWWW 
Reset  
Bit 76543210 
 MDATA_RXDATAX_RX  INTDIS_DMA AUTO_VALIDEPT_DISABL 
Access WWWWW 
Reset  

Bit 31 – SHRT_PCKT Short Packet Interrupt Disable

For IN endpoints: Never automatically add a zero length packet at end of DMA transfer.

For OUT endpoints:

ValueDescription
0

No effect.

1

Disable Short Packet Interrupt.

Bit 18 – BUSY_BANK Busy Bank Interrupt Disable

ValueDescription
0

No effect.

1

Disable Busy Bank Interrupt.

Bit 14 – ERR_FLUSH bank flush error Interrupt Disable

ValueDescription
0

No effect.

1

Disable Bank Flush Error Interrupt.

Bit 13 – ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Disable

ValueDescription
0

No effect.

1

Disable Error CRC ISO/Error Number of Transaction Interrupt.

Bit 12 – ERR_FL_ISO Error Flow Interrupt Disable

ValueDescription
0

No effect.

1

Disable Error Flow ISO Interrupt.

Bit 11 – TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Disable

ValueDescription
0

No effect.

1

Disable TX Packet Ready/Transaction Error Interrupt.

Bit 10 – TX_COMPLT Transmitted IN Data Complete Interrupt Disable

ValueDescription
0

No effect.

1

Disable Transmitted IN Data Complete Interrupt.

Bit 9 – RXRDY_TXKL Received OUT Data Interrupt Disable

ValueDescription
0

No effect.

1

Disable Received OUT Data Interrupt.

Bit 8 – ERR_OVFLW Overflow Error Interrupt Disable

ValueDescription
0

No effect.

1

Disable Overflow Error Interrupt.

Bit 7 – MDATA_RX MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)

ValueDescription
0

No effect.

1

Disable MDATA Interrupt.

Bit 6 – DATAX_RX DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)

ValueDescription
0

No effect.

1

Disable DATAx Interrupt.

Bit 3 – INTDIS_DMA Interrupts Disable DMA

ValueDescription
0

No effect.

1

Disable the “Interrupts Disable DMA”.

Bit 1 – AUTO_VALID Packet Auto-Valid Disable

ValueDescription
0

No effect.

1

Disable this bit to not automatically validate the current packet.

Bit 0 – EPT_DISABL Endpoint Disable

ValueDescription
0

No effect.

1

Disable endpoint.