41.6.10.4 Data OUT

  • Bulk OUT or Interrupt OUT

    Like data IN, data OUT packets are sent by the host during the data or the status stage of control transfer or during an interrupt/bulk/isochronous OUT transfer. Data buffers are sent packet by packet under the control of the application or under the control of the DMA channel.

  • Bulk OUT or Interrupt OUT: Receiving a Packet Under Application Control (Host to Device)

    Algorithm Description for Each Packet:

    • The application enables an interrupt on RXRDY_TXKL.
    • When an interrupt on RXRDY_TXKL is received, the application knows that UDPHS_EPTSTAx register BYTE_COUNT bytes have been received.
    • The application reads the BYTE_COUNT bytes from the endpoint.
    • The application clears RXRDY_TXKL.
      Note: If the application does not know the size of the transfer, it may not be a good option to use AUTO_VALID. Because if a zero-length-packet is received, the RXRDY_TXKL is automatically cleared by the AUTO_VALID hardware and if the endpoint interrupt is triggered, the software will not find its originating flag when reading the UDPHS_EPTSTAx register.

    Algorithm to Fill Several Packets

    • The application enables the interrupts of BUSY_BANK and AUTO_VALID.
    • When a BUSY_BANK interrupt is received, the application knows that all banks available for the endpoint have been filled. Thus, the application can read all banks available.

    If the application does not know the size of the receive buffer, instead of using the BUSY_BANK interrupt, the application must use RXRDY_TXKL.

  • Bulk OUT or Interrupt OUT: Sending a Buffer Using DMA (Host To Device)

To use the DMA setting, the AUTO_VALID field is mandatory.

See Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host) for more information.

DMA Configuration Example:

  1. First program UDPHS_DMAADDRESSx with the address of the buffer that should be transferred.
  2. Enable the interrupt of the DMA in the Interrupt Enable register (UDPHS_IEN).
  3. Program the DMA Channelx Control Register:
    • Size of buffer to be sent.
    • END_B_EN: Can be used for OUT packet truncation (discarding of unbuffered packet data) at the end of DMA buffer.
    • END_BUFFIT: Generate an interrupt when UDPHS_DMASTATUSx.BUFF_COUNT reaches 0.
    • END_TR_EN: End of transfer enable, the UDPHS device can put an end to the current DMA transfer, in case of a short packet.
    • END_TR_IT: End of transfer interrupt enable, an interrupt is sent after the last USB packet has been transferred by the DMA, if the USB transfer ended with a short packet. (Beneficial when the receive size is unknown.)
    • CHANN_ENB: Run and stop at end of buffer.

For OUT transfer, the bank will be automatically cleared by hardware when the application has read all the bytes in the bank (the bank is empty).

Note:
  1. When a zero-length-packet is received, UDPHS_EPTSTAx.RXRDY_TXKL is cleared automatically by AUTO_VALID, and the application knows of the end of buffer by the presence of the END_TR_IT.
  2. If the host sends a zero-length packet, and the endpoint is free, then the device sends an ACK. No data is written in the endpoint, the RXRDY_TXKL interrupt is generated, and the UDPHS_EPTSTAx.BYTE_COUNT field is null.
Figure 41-14. Data OUT Transfer for Endpoint with One Bank

Figure 41-15. Data OUT Transfer for an Endpoint with Two Banks

  • High Bandwidth Isochronous Endpoint OUT

    USB 2.0 supports individual High Speed isochronous endpoints that require data rates up to 192 Mb/s (24 MB/s): 3x1024 data bytes per microframe.

    To support such a rate, two or three banks may be used to buffer the three consecutive data packets. The microcontroller (or the DMA) should be able to empty the banks very rapidly (at least 24 MB/s on average).

    NB_TRANS field in UDPHS_EPTCFGx register = Number Of Transactions per Microframe.

    If NB_TRANS > 1 then it is High Bandwidth.

    Example:

    • If NB_TRANS = 3, the sequence should be either one of the following:
      • MData0
      • MData0/Data1
      • MData0/Data1/Data2
    • If NB_TRANS = 2, the sequence should be either one of the following:
      • MData0
      • MData0/Data1
    • If NB_TRANS = 1, the sequence should be:
      • Data0
Figure 41-16. Bank Management, Example of Three Transactions per Microframe

  • Isochronous Endpoint Handling: OUT Example

    The user can ascertain the bank status (free or busy), and the toggle sequencing of the data packet for each bank with the UDPHS_EPTSTAx register in the three fields as follows:

    • TOGGLESQ_STA: PID of the data stored in the current bank.
    • CURBK: Number of the bank currently being accessed by the microcontroller.
    • BUSY_BANK_STA: Number of busy bank.

    This is particularly useful in case of a missing data packet.

    If the inter-packet delay between the OUT token and the Data is greater than the USB standard, then the ISO-OUT transaction is ignored. (Payload data is not written, no interrupt is generated to the CPU.)

    If there is a data CRC (Cyclic Redundancy Check) error, the payload is, none the less, written in the endpoint. The UDPHS_EPTSTAx.ERR_CRC_NTR flag is set.

    If the endpoint is already full, the packet is not written in the DPRAM. The UDPHS_EPTSTAx.ERR_FL_ISO flag is set.

    If the payload data is greater than the maximum size of the endpoint, then the ERR_OVFLW flag is set. It is the task of the CPU to manage this error. The data packet is written in the endpoint (except the extra data).

    If the host sends a Zero Length Packet, and the endpoint is free, no data is written in the endpoint, the RXRDY_TXKL flag is set, and the UDPHS_EPTSTAx.BYTE_COUNT field is null.

    The FRCESTALL command bit is unused for an isochronous endpoint.

    Otherwise, payload data is written in the endpoint, the RXRDY_TXKL interrupt is generated and BYTE_COUNT is updated.