50.6.2 Serial Clock Phase and Polarity
All combinations of polarity and phase are available when QSPI operates in SPI mode (QSPI_MR.SMM=0).
In QSPI Serial Memory mode (QSPI_MR.SMM=1), only Mode 0 is supported.
The clock polarity is programmed with the CPOL bit in the QSPI Serial Clock register (QSPI_SCR). QSPI_SCR.CPHA programs the clock phase. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, the interfaced client must use the same parameter values to communicate.
The table below shows the four modes and corresponding parameter settings.
| QSPI Clock Mode | QSPI_SCR.CPOL | QSPI_SCR.CPHA | Host Shift QSCK Edge | Client Capture QSCK Edge | QSCK Inactive Level |
|---|---|---|---|---|---|
| 0 (QSPI, SPI) | 0 | 0 | Falling | Falling | Low |
| 1 (SPI) | 0 | 1 | Rising | Rising | Low |
| 2 (SPI) | 1 | 0 | Rising | Rising | High |
| 3 (SPI) | 1 | 1 | Falling | Falling | High |
The following figures show examples of data transfers.
