44.8.7 I2SC Interrupt Disable Register
The following configuration values are valid for all listed bit names of this
register:
0: No effect.
1: Clears the corresponding bit in I2SC_IMR.
| Name: | I2SC_IDR |
| Offset: | 0x18 |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | TXUR | TXRDY | | | RXOR | RXRDY | | |
| Access | | W | W | | | W | W | | |
| Reset | | – | – | | | – | – | | |
Bit 6 – TXUR Transmit Underflow Interrupt Disable
Bit 5 – TXRDY Transmit Ready Interrupt Disable
Bit 2 – RXOR Receiver Overrun Interrupt Disable
Bit 1 – RXRDY Receiver Ready Interrupt Disable
