17.4 Chip Setup

When the device is powered on, the Processor clock (PCK) and the Main System Bus clock (MCK) source is the 12 MHz fast RC oscillator.

The ROM code performs a low-level initialization that follows the steps described below:
  1. Stack setup for Arm supervisor mode.
  2. PLLA initialization
  3. Main System Bus clock selection: when the PLLA is stabilized, the Main System Bus clock source is switched from internal 12 MHz RC to PLLA. The PMC Status register is polled to wait for MCK Ready. PCK and MCK are now the Main clock.
  4. C Variable initialization: non zero-initialized data is initialized in the RAM (copy from ROM to RAM). Zero-initialized data is set to 0 in the RAM.
For clock frequencies, see the table Clock Frequencies during External Memory Boot Sequence.
Note: No external crystal or clock is needed during the external boot memories sequence. An external clock source is checked before the launch of the SAM-BA monitor to get a more accurate clock signal for USB.