44.6.4 I2S Reception and Transmission Sequence

As specified in the I2S protocol, data bits are left-justified in the word select time slot, with the MSB transmitted first, starting one clock period after the transition on the word select line.

Figure 44-2. I2S Reception and Transmission Sequence

Data bits are sent on the falling edge of the serial clock and sampled on the rising edge of the serial clock. The word select line indicates the channel in transmission, a low level for the left channel and a high level for the right channel.

The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing I2SC_MR.DATALENGTH.

If the time slot allows for more data bits than written in I2SC_MR.DATALENGTH, zeroes are appended to the transmitted data word or extra received bits are discarded.