47.8.7.7 SPI Multiple Data Access
For some operating modes, it is possible to reduce the number of accesses to FLEX_SPI_TDR/FLEX_SPI_RDR required to transfer an amount of data, by concatenating multiple data (8-bit or 9-bit to 16-bit) when the FIFO is enabled (FLEX_SPI_CR.FIFOEN=1) and fixed peripheral select is used (FLEX_SPI_MR.PS=0).
Up to two data can be written in one FLEX_SPI_TDR write access.
Up to four data can be read in one FLEX_SPI_RDR access.
When the FIFO is enabled, the number of data written in a single access to FLEX_SPI_TDR is only defined by the type of access.
| Config/Access | Byte | Halfword | Word |
|---|---|---|---|
| 8-bit to 16-bit | 1 | 1 | 2 |
When the FIFO is enabled, the number of data read in a single access to FLEX_SPI_RDR is defined by the type of access and the configuration of FLEX_SPI_CSR0.BITS.
| Config/Access | Byte | Halfword | Word |
|---|---|---|---|
| FLEX_SPI_CSR0.BITS=0 8-bit data |
1 | 2 | 4 |
| FLEX_SPI_CSR0.BITS>0 9-bit to 16-bit data |
1 | 1 | 2 |
Multiple data can be read from the Receive FIFO only in Client mode (FLEX_SPI_MR.MSTR=0).
The Transmit FIFO can be loaded with multiple data in the same FLEX_SPI_TDR access when FLEX_SPI_MR.PS=0.
Written/read data are always right-aligned, as described in sections SPI Receive Data Register (FIFO Multiple Data, 8-bit), SPI Receive Data Register (FIFO Multiple Data, 16-bit) and SPI Transmit Data Register (FIFO Multiple Data, 8- to 16-bit).
As an example, if the Transmit FIFO is empty and there are six data to send, either of the following write accesses may be performed:
- six FLEX_SPI_TDR-byte write accesses
- three FLEX_SPI_TDR-halfword write accesses
With a Receive FIFO containing six data, any of the following read accesses may be performed:
- six FLEX_SPI_RDR-byte read accesses
- three FLEX_SPI_RDR-halfword read accesses
- one FLEX_SPI_RDR-word read access and one FLEX_SPI_RDR-halfword read access