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Ultra-Low-Power Arm® Cortex®-A5 Core-Based MPU, Graphics Interface, Ethernet 10/100, IEEE®1588, CAN-FD, USB, AEC-Q100 Grade 2
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47
Flexible Serial Communication Controller (FLEXCOM)
47.8
SPI Functional Description
47.8.7
SPI FIFOs
47.8.7.4
Clearing/Flushing FIFOs
Description
Features
1
Configuration Summary
2
Block Diagram
3
Signal Description
4
Microchip Recommended Power Management Solutions
5
Automotive Quality Grade
6
Safety and Security Features
7
Pinout
8
Power Considerations
9
Memories
10
Event System
11
System Controller
12
Peripherals
13
Chip Identifier (CHIPID)
14
Cortex-A5 Processor (ARM)
15
L2 Cache Controller (L2CC)
16
Debug and Test Features
17
Standard Boot Strategies
18
CPU System Bus Matrix (CPUMX)
19
Matrix (H64MX/H32MX)
20
Special Function Registers (SFR)
21
Special Function Registers Backup (SFRBU)
22
Advanced Interrupt Controller (AIC)
23
Watchdog Timer (WDT)
24
Reset Controller (RSTC)
25
Shutdown Controller (SHDWC)
26
Periodic Interval Timer (PIT)
27
Real-time Clock (RTC)
28
System Controller Write Protection (SYSCWP)
29
Slow Clock Controller (SCKC)
30
Peripheral Touch Controller (PTC)
31
Low Power Asynchronous Receiver (RXLP)
32
Clock Generator
33
Power Management Controller (PMC)
34
Parallel Input/Output Controller (PIO)
35
External Memories
36
DDR-SDRAM Controller (MPDDRC)
37
Static Memory Controller (SMC)
38
DMA Controller (XDMAC)
39
LCD Controller (LCDC)
40
Ethernet MAC (GMAC)
41
USB Device High Speed Port (UDPHS)
42
USB Host High Speed Port (UHPHS)
43
Audio Class D Amplifier (CLASSD)
44
Inter-IC Sound Controller (I2SC)
45
Synchronous Serial Controller (SSC)
46
Two-wire Interface (TWIHS)
47
Flexible Serial Communication Controller (FLEXCOM)
47.1
Description
47.2
Embedded Characteristics
47.3
Block Diagram
47.4
I/O Lines Description
47.5
Product Dependencies
47.6
Register Accesses
47.7
USART Functional Description
47.8
SPI Functional Description
47.8.1
Modes of Operation
47.8.2
Data Transfer
47.8.3
Host Mode Operations
47.8.4
SPI Client Mode
47.8.5
SPI Comparison Function on Received Character
47.8.6
SPI Asynchronous and Partial Wake-up
47.8.7
SPI FIFOs
47.8.7.1
Overview
47.8.7.2
Sending Data with FIFO Enabled
47.8.7.3
Receiving Data with FIFO Enabled
47.8.7.4
Clearing/Flushing FIFOs
47.8.7.5
TXEMPTY, TDRE and RDRF Behavior
47.8.7.6
SPI Single Data Access
47.8.7.7
SPI Multiple Data Access
47.8.7.8
FIFO Pointer Error
47.8.7.9
FIFO Thresholds
47.8.7.10
FIFO Flags
47.8.8
SPI Register Write Protection
47.8.9
Local Loopback Test Mode
47.9
TWI Functional Description
47.10
Register Summary
48
Universal Asynchronous Receiver Transmitter (UART)
49
Serial Peripheral Interface (SPI)
50
Quad Serial Peripheral Interface (QSPI)
51
Secure Digital MultiMedia Card Controller (SDMMC)
52
Image Sensor Controller (ISC)
53
Controller Area Network (MCAN)
54
Timer Counter (TC)
55
Pulse Density Modulation Interface Controller (PDMIC)
56
Pulse Width Modulation Controller (PWM)
57
Secure Fuse Controller (SFC)
58
Integrity Check Monitor (ICM)
59
Advanced Encryption Standard Bridge (AESB)
60
Advanced Encryption Standard (AES)
61
Secure Hash Algorithm (SHA)
62
Triple Data Encryption Standard (TDES)
63
True Random Number Generator (TRNG)
64
Analog Comparator Controller (ACC)
65
Security Module (SECUMOD)
66
Analog-to-Digital Controller (ADC)
67
Electrical Characteristics
68
Mechanical Characteristics
69
Marking
70
Ordering Information
71
Revision History
Microchip Information
47.8.7.4 Clearing/Flushing FIFOs
Each FIFO can be cleared/flushed using FLEX_SPI_CR.TXFCLR/RXFCLR.
