14.6.4 Memory Access Sequence

When the processor generates a memory access, the MMU:

  1. Performs a lookup for the requested virtual address and current ASID and security state in the relevant instruction or data micro TLB.
  2. If there is a miss in the micro TLB, performs a lookup for the requested virtual address and current ASID and security state in the main TLB.
  3. If there is a miss in main TLB, performs a hardware translation table walk.

The MMU can be configured to perform hardware translation table walks in cacheable regions by setting the IRGN bits in Translation Table Base Register 0 and Translation Table Base Register 1. If the encoding of the IRGN bits is write-back, an L1 data cache lookup is performed and data is read from the data cache. If the encoding of the IRGN bits is write-through or non-cacheable, an access to external memory is performed. For more information, see Cortex-A5 Technical Reference Manual.

The MMU might not find a global mapping, or a mapping for the currently selected ASID, with a matching Non-secure TLB ID (NSTID) for the virtual address in the TLB. In this case, the hardware does a translation table walk if the translation table walk is enabled by the PD0 or PD1 bit in the Translation Table Base Control Register. If translation table walks are disabled, the processor returns a Section Translation fault. For more information, see Cortex-A5 Technical Reference Manual.

If the TLB finds a matching entry, it uses the information in the entry as follows:

  1. The access permission bits and the domain determine if the access is enabled. If the matching entry does not pass the permission checks, the MMU signals a memory abort. See the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition for a description of access permission bits, abort types and priorities, and for a description of the Instruction Fault Status Register (IFSR) and Data Fault Status Register (DFSR).
  2. The memory region attributes specified in both the TLB entry and the CP15 c10 remap registers determine if the access is
    • Secure or Non-secure
    • Shared or not
    • Normal memory, Device, or Strongly-ordered

    For more information, see Cortex-A5 Technical Reference Manual, Memory region remap.

  3. The TLB translates the virtual address to a physical address for the memory access.