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Ultra-Low-Power Arm® Cortex®-A5 Core-Based MPU, Graphics Interface, Ethernet 10/100, IEEE®1588, CAN-FD, USB, AEC-Q100 Grade 2
Ultra-Low-Power Arm® Cortex®-A5 Core-Based MPU, Graphics Interface, Ethernet 10/100, IEEE®1588, CAN-FD, USB, AEC-Q100 Grade 2
  1. Home
  2. 46 Two-wire Interface (TWIHS)
  3. 46.6 Functional Description
  4. 46.6.6 FIFOs
  5. 46.6.6.4 Sending/Receiving with FIFO Enabled in Client Mode
  • Description
  • Features
  • 1 Configuration Summary
  • 2 Block Diagram
  • 3 Signal Description
  • 4 Microchip Recommended Power Management Solutions
  • 5 Automotive Quality Grade
  • 6 Safety and Security Features
  • 7 Pinout
  • 8 Power Considerations
  • 9 Memories
  • 10 Event System
  • 11 System Controller
  • 12 Peripherals
  • 13 Chip Identifier (CHIPID)
  • 14 Cortex-A5 Processor (ARM)
  • 15 L2 Cache Controller (L2CC)
  • 16 Debug and Test Features
  • 17 Standard Boot Strategies
  • 18 CPU System Bus Matrix (CPUMX)
  • 19 Matrix (H64MX/H32MX)
  • 20 Special Function Registers (SFR)
  • 21 Special Function Registers Backup (SFRBU)
  • 22 Advanced Interrupt Controller (AIC)
  • 23 Watchdog Timer (WDT)
  • 24 Reset Controller (RSTC)
  • 25 Shutdown Controller (SHDWC)
  • 26 Periodic Interval Timer (PIT)
  • 27 Real-time Clock (RTC)
  • 28 System Controller Write Protection (SYSCWP)
  • 29 Slow Clock Controller (SCKC)
  • 30 Peripheral Touch Controller (PTC)
  • 31 Low Power Asynchronous Receiver (RXLP)
  • 32 Clock Generator
  • 33 Power Management Controller (PMC)
  • 34 Parallel Input/Output Controller (PIO)
  • 35 External Memories
  • 36 DDR-SDRAM Controller (MPDDRC)
  • 37 Static Memory Controller (SMC)
  • 38 DMA Controller (XDMAC)
  • 39 LCD Controller (LCDC)
  • 40 Ethernet MAC (GMAC)
  • 41 USB Device High Speed Port (UDPHS)
  • 42 USB Host High Speed Port (UHPHS)
  • 43 Audio Class D Amplifier (CLASSD)
  • 44 Inter-IC Sound Controller (I2SC)
  • 45 Synchronous Serial Controller (SSC)
  • 46 Two-wire Interface (TWIHS)
    • 46.1 Description
    • 46.2 Embedded Characteristics
    • 46.3 List of Abbreviations
    • 46.4 Block Diagram
    • 46.5 Product Dependencies
    • 46.6 Functional Description
      • 46.6.1 Transfer Format
      • 46.6.2 Modes of Operation
      • 46.6.3 Host Mode
      • 46.6.4 Multi-Host Mode
      • 46.6.5 Client Mode
      • 46.6.6 FIFOs
        • 46.6.6.1 Overview
        • 46.6.6.2 Sending Data with FIFO Enabled
        • 46.6.6.3 Receiving Data with FIFO Enabled
        • 46.6.6.4 Sending/Receiving with FIFO Enabled in Client Mode
        • 46.6.6.5 Clearing/Flushing FIFOs
        • 46.6.6.6 TXRDY and RXRDY Behavior
        • 46.6.6.7 Single Data Mode
        • 46.6.6.8 Multiple Data Mode
        • 46.6.6.9 Transmit FIFO Lock
        • 46.6.6.10 FIFO Pointer Error
        • 46.6.6.11 FIFO Thresholds
        • 46.6.6.12 FIFO Flags
      • 46.6.7 TWIHS Comparison Function on Received Character
      • 46.6.8 Register Write Protection
    • 46.7 Register Summary
  • 47 Flexible Serial Communication Controller (FLEXCOM)
  • 48 Universal Asynchronous Receiver Transmitter (UART)
  • 49 Serial Peripheral Interface (SPI)
  • 50 Quad Serial Peripheral Interface (QSPI)
  • 51 Secure Digital MultiMedia Card Controller (SDMMC)
  • 52 Image Sensor Controller (ISC)
  • 53 Controller Area Network (MCAN)
  • 54 Timer Counter (TC)
  • 55 Pulse Density Modulation Interface Controller (PDMIC)
  • 56 Pulse Width Modulation Controller (PWM)
  • 57 Secure Fuse Controller (SFC)
  • 58 Integrity Check Monitor (ICM)
  • 59 Advanced Encryption Standard Bridge (AESB)
  • 60 Advanced Encryption Standard (AES)
  • 61 Secure Hash Algorithm (SHA)
  • 62 Triple Data Encryption Standard (TDES)
  • 63 True Random Number Generator (TRNG)
  • 64 Analog Comparator Controller (ACC)
  • 65 Security Module (SECUMOD)
  • 66 Analog-to-Digital Controller (ADC)
  • 67 Electrical Characteristics
  • 68 Mechanical Characteristics
  • 69 Marking
  • 70 Ordering Information
  • 71 Revision History
  • Microchip Information

46.6.6.4 Sending/Receiving with FIFO Enabled in Client Mode

See sections 46.6.6.2 Sending Data with FIFO Enabled and 46.6.6.3 Receiving Data with FIFO Enabled for details.

Figure 46-49. Sending/Receiving Data with FIFO Enabled in Client Mode
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