23.5.2 Watchdog Timer Mode Register
Write access to this register has no effect if the LOCKMR command is issued in WDT_CR (unlocked on hardware reset).
The WDT_MR register values must not be modified within three slow clock periods following a restart of the watchdog performed by a write access in WDT_CR. Any modification will cause the watchdog to trigger an end of period earlier than expected.
| Name: | WDT_MR |
| Offset: | 0x04 |
| Reset: | 0x3FFF2FFF |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WDIDLEHLT | WDDBGHLT | WDD[11:8] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WDD[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WDDIS | WDRSTEN | WDFIEN | WDV[11:8] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 1 | 0 | 1 | 1 | 1 | 1 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WDV[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bit 29 – WDIDLEHLT Watchdog Idle Halt
| Value | Description |
|---|---|
| 0 | The watchdog runs when the system is in idle state. |
| 1 | The watchdog stops when the system is in idle state. |
Bit 28 – WDDBGHLT Watchdog Debug Halt
| Value | Description |
|---|---|
| 0 | The watchdog runs when the processor is in debug state. |
| 1 | The watchdog stops when the processor is in debug state. |
Bits 27:16 – WDD[11:0] Watchdog Delta Value
Defines the permitted range for reloading the Watchdog Timer.
If the Watchdog Timer value is less than or equal to WDD, setting bit WDT_CR.WDRSTT restarts the timer.
If the Watchdog Timer value is greater than WDD, setting bit WDT_CR.WDRSTT causes a watchdog error.
Bit 15 – WDDIS Watchdog Disable
| Value | Description |
|---|---|
| 0 | Enables the Watchdog Timer. |
| 1 | Disables the Watchdog Timer. |
Bit 13 – WDRSTEN Watchdog Reset Enable
| Value | Description |
|---|---|
| 0 | A watchdog fault (underflow or error) has no effect on the resets. |
| 1 | A watchdog fault (underflow or error) triggers a watchdog reset. |
Bit 12 – WDFIEN Watchdog Fault Interrupt Enable
| Value | Description |
|---|---|
| 0 | A watchdog fault (underflow or error) has no effect on interrupt. |
| 1 | A watchdog fault (underflow or error) asserts interrupt. |
Bits 11:0 – WDV[11:0] Watchdog Counter Value
Defines the value loaded in the 12-bit watchdog counter.