24.5.2 Reset Controller Status Register
- 0x00000100 only when VDDCORE is rising
- 0x00000000 when both power supplies VDDCORE and VDDBU are rising (backup reset)
| Name: | RSTC_SR |
| Offset: | 0x04 |
| Reset: | See Note |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SRCMP | NRSTL | ||||||||
| Access | R | R | |||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RSTTYP[2:0] | |||||||||
| Access | R | R | R | ||||||
| Reset | |||||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| URSTS | |||||||||
| Access | R | ||||||||
| Reset |
Bit 17 – SRCMP Software Reset Command in Progress
| Value | Description |
|---|---|
| 0 | No software command is being performed by the RSTC. The RSTC is ready for a software command. |
| 1 | A software reset command is being performed by the RSTC. The RSTC is busy. |
Bit 16 – NRSTL NRST Pin Level
Records the level of the NRST pin sampled on each Main system bus clock (MCK) rising edge.
Bits 10:8 – RSTTYP[2:0] Reset Type
Reports the cause of the last processor reset. Reading RSTC_SR does not reset this field.
| Value | Name | Description |
|---|---|---|
| 0 | GENERAL_RST | Both VDDCORE and VDDBU rising |
| 1 | WKUP_RST | VDDCORE rising |
| 2 | WDT_RST | Watchdog fault occurred |
| 3 | SOFT_RST | Processor reset required by the software |
| 4 | USER_RST | NRST pin detected low |
| 5 | – | Reserved |
| 6 | – | Reserved |
| 7 | SLCK_XTAL_RST | 32.768 kHz Crystal Oscillator Failure Detection Reset |
Bit 0 – URSTS User Reset Status
| Value | Description |
|---|---|
| 0 | No high-to-low edge on NRST happened since the last read of RSTC_SR. |
| 1 | At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. Reading the RSTC_SR resets URSTS and clears the interrupt. |