19.3.2 Matrix Clients
The H64MX manages 15 clients. Each client has its own arbiter providing a dedicated arbitration per client.
| Client No. | Description | TrustZone Access Management |
|---|---|---|
| 0 | Bridge from H64MX to H32MX | Not applicable |
| 1 | H64MX Peripheral Bridge | HSEL0: not applicable |
| SDMMC0 | HSEL1: Internal Securable to Peripheral: 1 region(1) | |
| SDMMC1 | HSEL2: Internal Securable to Peripheral: 1 region(1) | |
| 2 | DDR2 Port 0 - AESB | Scalable Securable: 4 regions(2) |
| 3 | DDR2 Port 1 | Scalable Securable: 4 regions(2) |
| 4 | DDR2 Port 2 | Scalable Securable: 4 regions(2) |
| 5 | DDR2 Port 3 | Scalable Securable: 4 regions(2) |
| 6 | DDR2 Port 4 | Scalable Securable: 4 regions(2) |
| 7 | DDR2 Port 5 | Scalable Securable: 4 regions(2) |
| 8 | DDR2 Port 6 | Scalable Securable: 4 regions(2) |
| 9 | DDR2 Port 7 | Scalable Securable: 4 regions(2) |
| 10 | Internal SRAM 128K | Internal Securable: 1 region |
| 11 | Internal SRAM 128K (Cache L2) | Internal Securable: 1 region |
| 12 | QSPI0 | Internal Securable: 1 region |
| 13 | QSPI1 | Internal Securable: 1 region |
| 14 | AESB | Not applicable |
Note:
- For each SDMMCx, see Security Types of SDMMC System Bus Clients for Internal
Securable to Peripheral type configuration. A consistent configuration must be done
for:
- the client port,
- MATRIX_SPSELSR for the general interrupt and the host port,
- MATRIX_SPSELSR for the TIMER interrupt.
- For consistency, each DDR2 port must have the same TrustZone access management configuration.
