15.4.1 Double Linefill Issuing
The L2CC cache line length is 32-byte. Therefore, by default, on each L2 cache miss, the L2CC issues 32-byte linefills, 4 x 64-bit read bursts, to the L3 memory system. The L2CC can issue 64-byte linefills, 8 x 64-bit read bursts, on an L2 cache miss. When the L2CC is waiting for the data from L3, it performs a lookup on the second cache line targeted by the 64-byte linefill. If it misses, data corresponding to the second cache line are allocated to the L2 cache. If it hits, data corresponding to the second cache line are discarded.
The user can control this feature using the DLEN, DLFWRDIS and DLEN bits of the L2CC Prefetch Control Register. The IDLEN and DLFWRDIS bits are only used if the user sets the DLEN bit HIGH. The table below shows the behavior of the L2CC host ports, depending on the configuration chosen by the user.
| Bit 30 DLEN |
Bit 27 DLFWRDIS |
Bit 23 IDLEN |
Original Read Address from L1 | Read Address to L3 | CPU System Bus Burst Type | CPU System Bus Burst Length | Targeted Cache Lines |
|---|---|---|---|---|---|---|---|
| 0 | 0 or 1 | 0 or 1 | 0x00 | 0x00 | WRAP | 0x3, 4x64-bit | 0x00 |
| 0 | 0 or 1 | 0 or 1 | 0x20 | 0x20 | WRAP | 0x3, 4x64-bit | 0x20 |
| 1 | 0 or 1 | 0 | 0x00 | 0x00 | WRAP | 0x7, 8x64-bit | 0x00 and 0x20 |
| 1 | 1 | 0 | 0x08 or 0x10 or 0x18 | 0x08 | WRAP | 0x3, 4x64-bit | 0x00 |
| 1 | 0 | 0 | 0x08 or 0x10 or 0x18 | 0x00 | WRAP | 0x7, 8x64-bit | 0x00 and 0x20 |
| 1 | 0 or 1 | 0 | 0x20 | 0x20 | WRAP | 0x7, 8x64-bit | 0x00 and 0x20 |
| 1 | 1 | 0 | 0x28 or 0x30 or 0x38 | 0x28 | WRAP | 0x3, 4x64-bit | 0x20 |
| 1 | 0 | 0 | 0x28 or 0x30 or 0x38 | 0x20 | WRAP | 0x7, 8x64-bit | 0x00 and 0x20 |
| 1 | 0 or 1 | 1 | 0x00 | 0x00 | INCR or WRAP | 0x7, 8x64-bit | 0x00 and 0x20 |
| 1 | 1 | 1 | 0x08 or 0x10 or 0x18 | 0x08 | WRAP | 0x3, 4x64-bit | 0x00 |
| 1 | 0 | 1 | 0x08 or 0x10 or 0x18 | 0x00 | INCR or WRAP | 0x7, 8x64-bit | 0x00 and 0x20 |
| 1 | 0 or 1 | 1 | 0x20 | 0x20 | INCR | 0x7, 8x64-bit | 0x20 and 0x40 |
| 1 | 1 | 1 | 0x28 or 0x30 or 0x38 | 0x28 | WRAP | 0x3, 4x64-bit | 0x20 |
| 1 | 0 | 1 | 0x28 or 0x30 or 0x38 | 0x20 | INCR | 0x7, 8x64-bit | 0x20 and 0x40 |
- Double linefills are not issued for prefetch reads if exclusive cache configuration is enabled.
- Double linefills are not launched when crossing a 4-Kbyte boundary.
- Double linefills only occur if a WRAP4 or an INCR4 64-bit transaction is received on the client ports. This transaction is most commonly seen as a result of a cache linefill in a host, but can be produced by a host when accessing memory marked as inner non-cacheable.