15.5.28 L2CC Prefetch Control Register

The L2CC always issues 4x64-bit read bursts to L3 on reads that miss in the L2 cache. This is the default value.

The L2CC issues 8x64-bit read bursts to L3 on reads that miss in the L2 cache.

Instruction prefetching is disabled. This is the default value.

Instruction prefetching is enabled.

Data prefetching is disabled. This is the default value.

Data prefetching is enabled.

Double linefill on WRAP read is enabled. This is the default value.

Double linefill on WRAP read is disabled.

Note: This bit can only be used if the DLEN bit is set HIGH. See Double Linefill Issuing for details on double linefill functionality.

The L2CC does not discard prefetch reads issued to L3. This is the default value.

The L2CC discards prefetch reads issued to L3 when there is a resource conflict with explicit reads.

The L2CC does not issue INCR 8x64-bit read bursts to L3 on reads that miss in the L2 cache. This is the default value.

The L2CC can issue INCR 8x64-bit read bursts to L3 on reads that miss in the L2 cache.

Read and write portions of a non-cacheable exclusive sequence have the same CPU system bus ID when issued to L3. This is the default value.

Read and write portions of a non-cacheable exclusive sequence do not have the same CPU system bus ID when issued to L3.