52.7.10 ISC Clock Configuration Register

Name:	ISC_CLKCFG
Offset:	0x24
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
							MCSEL[1:0]
Access							R/W	R/W
Reset							0	0


Bit	23	22	21	20	19	18	17	16
	MCDIV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
								ICSEL
Access								R/W
Reset								0


Bit	7	6	5	4	3	2	1	0
	ICDIV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 25:24 – MCSEL[1:0] Camera Sensor Reference Clock Selection

Value	Description
0	hclock is selected.
1	iscclk is selected.
2	gck is selected.

Bits 23:16 – MCDIV[7:0] Camera Sensor Reference Clock Divider

f_{mc} = \frac{f_{mcref}}{MCDIV + 1}

Bit 8 – ICSEL ISP Clock Selection

Value	Description
0	hclock is selected.
1	hclock is selected.

Bits 7:0 – ICDIV[7:0] ISP Clock Divider

f_{cc} = \frac{f_{ccref}}{ICDIV + 1}