7.3 Internal Writing Methodology

The AT24CM02 incorporates a built-in error detection and correction (EDC) logic scheme. The EEPROM array is internally organized as a group of four connected 8-bit bytes plus an additional six ECC (Error Correction Code) bits of EEPROM. These 38 bits are referred to as the internal physical data word. During a read sequence, the EDC logic compares each 4-byte physical data word with its corresponding six ECC bits. If a single bit out of the 4-byte region reads incorrectly, the EDC logic will detect the bad bit and replace it with a correct value before the data is serially clocked out. This architecture significantly improves the reliability of the AT24CM02 compared to an implementation that does not utilize EDC.

It is important to note that data is always physically written to the part at the internal physical data word level, regardless of the number of bytes written. Writing single bytes is still possible with the byte write operation, but internally, the other three bytes within that 4-byte location where the single byte was written, along with the six ECC bits, will be updated. Due to this architecture, the AT24CM02 EEPROM write endurance is rated at the internal physical data word level (4-byte word). The system designer needs to optimize the application writing algorithms to observe these internal word boundaries in order to reach the endurance rating.