7.6 Write Protection

The AT24CM02 utilizes a hardware data protection scheme that allows the user to write‑protect the entire memory contents when the WP pin is at V_CC (or a valid V_IH). No write protection will be set if the WP pin is at GND or left floating.

The status of the WP pin is sampled at the Stop condition for every byte write or page write operation prior to the start of an internally self‑timed write cycle. Changing the WP pin state after the Stop condition has been sent will not alter or interrupt the execution of the write cycle. The WP pin state must be valid with respect to the associated setup (tSU.WP) and hold (tHD.WP) timing as shown in Figure 7-5 below. The WP setup time is the amount of time that the WP state must be stable before the Stop condition is issued. The WP hold time is the amount of time after the Stop condition that the WP must remain stable (see Table 4-3, AC Characteristics,” for timing specs for tHD.WP and tSU.WP).

If an attempt is made to write to the device while the WP pin has been asserted, the device will acknowledge the device address, word address and data bytes. However, no write cycle will occur when the Stop condition is issued. The device will immediately be ready to accept a new read or write command.