6.2 CONFIG2
Note:
- Once protection is enabled through ICSP™ or a self-write, it can only be reset through a Bulk Erase.
| Name: | CONFIG2 |
| Offset: | 30 0001h |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FCMENS | FCMENP | FCMEN | CSWEN | BBEN | PR1WAY | CLKOUTEN | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Bit 7 – FCMENS Fail-Safe Clock Monitor Enable - Secondary XTAL Enable
| Value | Description |
|---|---|
| 1 | Fail-Safe Clock Monitor enabled; the timer will flag the FSCMS bit and OSFIF interrupt on SOSC failure |
| 0 | Fail-Safe Clock Monitor disabled |
Bit 6 – FCMENP Fail-Safe Clock Monitor Enable - Primary XTAL Enable
| Value | Description |
|---|---|
| 1 | Fail-Safe Clock Monitor enabled; the timer will flag the FSCMP bit and OSFIF interrupt on EXTOSC failure |
| 0 | Fail-Safe Clock Monitor disabled |
Bit 5 – FCMEN Fail-Safe Clock Monitor Enable
| Value | Description |
|---|---|
| 1 | Fail-Safe Clock Monitor enabled |
| 0 | Fail-Safe Clock Monitor disabled |
Bit 3 – CSWEN Clock Switch Enable
| Value | Description |
|---|---|
| 1 | Writing to NOSC and NDIV is allowed |
| 0 | The NOSC and NDIV bits cannot be changed by user software |
Bit 2 – BBEN Boot Block Enable(1)
| Value | Description |
|---|---|
| 1 | Boot Block is disabled |
| 0 | Boot Block is enabled |
Bit 1 – PR1WAY PRLOCKED One-Way Set Enable
| Value | Description |
|---|---|
| 1 | The PRLOCKED bit can be cleared and set only once; Priority registers remain locked after one clear/set cycle |
| 0 | The PRLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence) |
Bit 0 – CLKOUTEN Clock Out Enable
If FEXTOSC = HS, XT, LP, then this bit is ignored.
Otherwise:
| Value | Description |
|---|---|
| 1 | CLKOUT function is disabled; I/O function on OSC2 |
| 0 | CLKOUT function is enabled; FOSC/4 clock appears at OSC2 |