16.8.3 Interrupt Flag Status and Clear
| Name: | INTFLAG |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| [19:12] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| [11:4] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| [3:0] | B33SRDY | BOD33DET | BOD33RDY | DFLLRCS | |||||
| Access | R | R | R | R | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DFLLLCKC | DFLLLCKF | DFLLOOB | DFLLRDY | OSC8MRDY | OSC32KRDY | XOSC32KRDY | XOSCRDY | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:12 – [19:0] Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
Bit 11 – B33SRDY BOD33 Synchronization Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the BOD33 Synchronization Ready bit in the Status register (PCLKSR.B33SRDY) and will generate an interrupt request if INTENSET.B33SRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the BOD33 Synchronization Ready interrupt flag
Bit 10 – BOD33DET BOD33 Detection
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the BOD33 Detection bit in the Status register (PCLKSR.BOD33DET) and will generate an interrupt request if INTENSET.BOD33DET is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the BOD33 Detection interrupt flag.
Bit 9 – BOD33RDY BOD33 Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the BOD33 Ready bit in the Status register (PCLKSR.BOD33RDY) and will generate an interrupt request if INTENSET.BOD33RDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the BOD33 Ready interrupt flag.
Bit 8 – DFLLRCS DFLL Reference Clock Stopped
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Reference Clock Stopped bit in the Status register (PCLKSR.DFLLRCS) and will generate an interrupt request if INTENSET.DFLLRCS is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DFLL Reference Clock Stopped interrupt flag.
Bit 7 – DFLLLCKC DFLL Lock Coarse
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Lock Coarse bit in the Status register (PCLKSR.DFLLLCKC) and will generate an interrupt request if INTENSET.DFLLLCKC is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DFLL Lock Coarse interrupt flag.
Bit 6 – DFLLLCKF DFLL Lock Fine
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Lock Fine bit in the Status register (PCLKSR.DFLLLCKF) and will generate an interrupt request if INTENSET.DFLLLCKF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DFLL Lock Fine interrupt flag.
Bit 5 – DFLLOOB DFLL Out Of Bounds
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Out Of Bounds bit in the Status register (PCLKSR.DFLLOOB) and will generate an interrupt request if INTENSET.DFLLOOB is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DFLL Out Of Bounds interrupt flag.
Bit 4 – DFLLRDY DFLL Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Ready bit in the Status register (PCLKSR.DFLLRDY) and will generate an interrupt request if INTENSET.DFLLRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DFLL Ready interrupt flag.
Bit 3 – OSC8MRDY OSC8M Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the OSC8M Ready bit in the Status register (PCLKSR.OSC8MRDY) and will generate an interrupt request if INTENSET.OSC8MRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the OSC8M Ready interrupt flag.
Bit 2 – OSC32KRDY OSC32K Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the OSC32K Ready bit in the Status register (PCLKSR.OSC32KRDY) and will generate an interrupt request if INTENSET.OSC32KRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the OSC32K Ready interrupt flag.
Bit 1 – XOSC32KRDY XOSC32K Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the XOSC32K Ready bit in the Status register (PCLKSR.XOSC32KRDY) and will generate an interrupt request if INTENSET.XOSC32KRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the XOSC32K Ready interrupt flag.
Bit 0 – XOSCRDY XOSC Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the XOSC Ready bit in the Status register (PCLKSR.XOSCRDY) and will generate an interrupt request if INTENSET.XOSCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the XOSC Ready interrupt flag.