18.8.9 Interrupt Enable Clear - MODE1
| Name: | INTENCLR |
| Offset: | 0x06 |
| Reset: | 0x00 |
| Property: | Write-Protected |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OVF | SYNCRDY | CMPx | CMPx | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 7 – OVF Overflow Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt.
| Value | Description |
|---|---|
| 0 | The Overflow interrupt is disabled. |
| 1 | The Overflow interrupt is enabled, and an interrupt request will be generated when the Overflow interrupt flag is set. |
Bit 6 – SYNCRDY Synchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and disable the corresponding interrupt.
| Value | Description |
|---|---|
| 0 | The Synchronization Ready interrupt is disabled. |
| 1 | The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the Synchronization Ready interrupt flag is set. |
Bits 1,0 – CMPx Compare x Interrupt Enable [x=1:0]
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Compare x Interrupt Enable bit and disable the corresponding interrupt.
| Value | Description |
|---|---|
| 0 | The Compare x interrupt is disabled. |
| 1 | The Compare x interrupt is enabled, and an interrupt request will be generated when the Compare x interrupt flag is set. |