18.8.1 Control - MODE0
| Name: | CTRL |
| Offset: | 0x00 |
| Reset: | 0x0000 |
| Property: | Enable-Protected, Write-Protected, Write-Synchronized |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PRESCALER[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MATCHCLR | MODE[1:0] | ENABLE | SWRST | ||||||
| Access | R/W | R/W | R/W | R/W | W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bits 11:8 – PRESCALER[3:0] Prescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT).
These bits are not synchronized.
| PRESCALER[3:0] | Name | Description |
|---|---|---|
| 0x0 | DIV1 | CLK_RTC_CNT = GCLK_RTC/1 |
| 0x1 | DIV2 | CLK_RTC_CNT = GCLK_RTC/2 |
| 0x2 | DIV4 | CLK_RTC_CNT = GCLK_RTC/4 |
| 0x3 | DIV8 | CLK_RTC_CNT = GCLK_RTC/8 |
| 0x4 | DIV16 | CLK_RTC_CNT = GCLK_RTC/16 |
| 0x5 | DIV32 | CLK_RTC_CNT = GCLK_RTC/32 |
| 0x6 | DIV64 | CLK_RTC_CNT = GCLK_RTC/64 |
| 0x7 | DIV128 | CLK_RTC_CNT = GCLK_RTC/128 |
| 0x8 | DIV256 | CLK_RTC_CNT = GCLK_RTC/256 |
| 0x9 | DIV512 | CLK_RTC_CNT = GCLK_RTC/512 |
| 0xA | DIV1024 | CLK_RTC_CNT = GCLK_RTC/1024 |
| 0xB-0xF | Reserved |
Bit 7 – MATCHCLR Clear on Match
This bit is valid only in Mode 0 and Mode 2.
This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | The counter is not cleared on a Compare/Alarm 0 match. |
| 1 | The counter is cleared on a Compare/Alarm 0 match. |
Bits 3:2 – MODE[1:0] Operating Mode
These bits define the operating mode of the RTC.
These bits are not synchronized.
| MODE[1:0] | Name | Description |
|---|---|---|
| 0x0 | COUNT32 | Mode 0: 32-bit Counter |
| 0x1 | COUNT16 | Mode 1: 16-bit Counter |
| 0x2 | CLOCK | Mode 2: Clock/Calendar |
| 0x3 | Reserved |
Bit 1 – ENABLE Enable
Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
This bit is not enable-protected.
| Value | Description |
|---|---|
| 0 | The peripheral is disabled or being disabled. |
| 1 | The peripheral is enabled or being enabled. |
Bit 0 – SWRST Software Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.
Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete.
This bit is not enable-protected.
| Value | Description |
|---|---|
| 0 | There is no reset operation ongoing. |
| 1 | The reset operation is ongoing. |