30.8.5 Interrupt Enable Set

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x05
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
      SYNCRDYEMPTYUNDERRUN 
Access R/WR/WR/W 
Reset 000 

Bit 2 – SYNCRDY Synchronization Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Synchronization Ready Interrupt Enable bit, which disables the Synchronization Ready interrupt.

ValueDescription
0 The Synchronization Ready interrupt is disabled.
1 The Synchronization Ready interrupt is enabled.

Bit 1 – EMPTY Data Buffer Empty Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Data Buffer Empty Interrupt Enable bit, which enables the Data Buffer Empty interrupt.

ValueDescription
0 The Data Buffer Empty interrupt is disabled.
1 The Data Buffer Empty interrupt is enabled.

Bit 0 – UNDERRUN Underrun Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Data Buffer Underrun Interrupt Enable bit, which enables the Data Buffer Underrun interrupt.

ValueDescription
0 The Data Buffer Underrun interrupt is disabled.
1 The Data Buffer Underrun interrupt is enabled.