26.8.5 Interrupt Flag Status and Clear

Name: INTFLAG
Offset: 0x0E
Reset: 0x00
Property: -

Bit 76543210 
      DRDYAMATCHPREC 
Access R/WR/WR/W 
Reset 000 

Bit 2 – DRDY Data Ready

This flag is set when a I2C Client byte transmission is successfully completed.

The flag is cleared by hardware when either:

  • Writing to the DATA register.
  • Reading the DATA register with smart mode enabled.
  • Writing a valid command to the CMD register.

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear the Data Ready interrupt flag.

Bit 1 – AMATCH Address Match

This flag is set when the I2C Client address match logic detects that a valid address has been received.

The flag is cleared by hardware when CTRL.CMD is written.

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear the Address Match interrupt flag. When cleared, an ACK/NACK will be sent according to CTRLB.ACKACT.

Bit 0 – PREC Stop Received

This flag is set when a stop condition is detected for a transaction being processed. A stop condition detected between a bus Host and another Client will not set this flag, unless the PMBus Group Command is enabled in the Control B register (CTRLB.GCMD=1).

This flag is cleared by hardware after a command is issued on the next address match.

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear the Stop Received interrupt flag.