27.11 Register Summary for 32-bit Registers


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	CTRLA	7:0		WAVEGEN[1:0]			MODE[1:0]		ENABLE	SWRST
0x00	CTRLA	15:8			PRESCSYNC[1:0]		RUNSTDBY	PRESCALER[2:0]
0x02	READREQ	7:0				ADDR[4:0]
0x02	READREQ	15:8	RREQ	RCONT
0x04	CTRLBCLR	7:0	CMD[1:0]					ONESHOT		DIR
0x05	CTRLBSET	7:0	CMD[1:0]					ONESHOT		DIR
0x06	CTRLC	7:0			CPTEN1	CPTEN0			INVEN1	INVEN0
0x07	Reserved
0x08	DBGCTRL	7:0								DBGRUN
0x09	Reserved
0x0A	EVCTRL	7:0			TCEI	TCINV		EVACT[2:0]
0x0A	EVCTRL	15:8			MCEO1	MCEO0				OVFEO
0x0C	INTENCLR	7:0			MC1	MC0	SYNCRDY		ERR	OVF
0x0D	INTENSET	7:0			MC1	MC0	SYNCRDY		ERR	OVF
0x0E	INTFLAG	7:0			MC1	MC0	SYNCRDY		ERR	OVF
0x0F	STATUS	7:0	SYNCBUSY			SLAVE	STOP
0x10	COUNT	7:0	COUNT[7:0]
		15:8	COUNT[15:8]
		23:16	COUNT[23:16]
		31:24	COUNT[31:24]
0x14 ... 0x17	Reserved
0x18	CC0	7:0	CC[7:0]
		15:8	CC[15:8]
		23:16	CC[23:16]
		31:24	CC[31:24]
0x1C	CC1	7:0	CC[7:0]
		15:8	CC[15:8]
		23:16	CC[23:16]
		31:24	CC[31:24]