33.9.3 Digital-Frequency Locked Loop (DFLL48M) Characteristics
| Symbol | Parameter | Conditions | Min. | Typ. | Max. | Units |
|---|---|---|---|---|---|---|
| fOUT | Average Output frequency | fREF = XOSC32K 32.768 kHz | 47 | 48 | 49 | MHz |
| fREF | Reference frequency | - | 0.732 | 32.768 | 35.1 | kHz |
| Jitter | Period jitter | fREF = XOSC32K 32.768 kHz | - | - | 0.84 | ns |
| IDFLL | Power consumption on VDDIN | fREF = XOSC32K 32.768 kHz | - | 292 | - | μA |
| tLOCK | Lock time | fREF = XOSC32K 32.768 kHz DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.CCDIS = 1 DFLLMUL.FSTEP = 10 | 100 | 200 | 500 | μs |
| Quick lock disabled, Chill cycle disabled, CSTEP = 3,FSTEP = 1, fREF = XOSC32K 32.768 kHz | - | 600 | - |
Note: 1. Refer to the revision C/revision B errata pertaining to the DFLL48M.
2. All parts are tested in production to be able to use the DFLL as main CPU clock whether in DFLL closed-loop mode with an external OSC reference or in DFLL closed-loop mode using the internal OSC8M (only applicable for revision C).